Motorola MPC8240 User Manual page 397

2
10.1.4 I C Block Diagram
The reset state of the I
programmed to be a master or to respond to a slave transmitter address, the I
defaults to slave receiver operation. Figure 10-1 shows a block diagram of the I
Address & Control
addr_decode
addr_reg
Clock
Control
Input Sync
2
10.2 I C Protocol
2
A standard I C transfer consists of four parts:
1. START condition
2. Slave target address transmission
3. Data transfer
4. STOP condition
Figure 10-2 shows the interaction of these four parts and the calling address, data byte, and
new calling address components of the I
described in the following subsections.
2
C interface is as a slave receiver. Thus, when not explicitly
freq_reg control_reg
START,
STOP &
Arbitration
Control
SCL
2
Figure 10-1. I C Interface Block Diagram
Chapter 10. I
Interrupt Data
data_mux
status_reg data_reg
In/Out Data
Shift Register
Address
Compare
SDA
2
C protocol. The details of the protocol are
2
C Interface
2
I C Protocol
2
C unit always
2
C unit.
10-3