Power Management Configuration Register 2 (Pmcr2)—0X72 - Motorola MPC8240 User Manual

PCI_HOLD_DELAY[0–2]
DLL_EXTEND
Figure 4-6. Power Management Configuration Register 2 (PMCR2)—0x72
Table 4-16 describes the bits of PMCR2.
Table 4-16. Power Management Configuration Register 2—0x72
Bits Name
msb 7 DLL_EXTEND
6–4 PCI_HOLD_DEL xx0
3 —
2 PLL_SLEEP
1 —
0 SHARED_MCP
Peripheral Logic Power Management Configuration Registers (PMCRs)
7 6
Reset
Value
0 This bit can be used to shift the lock-range of the DLL by half of a PCI clock
cycle. See the MPC8240 Hardware Specification for more information on the
use of the DLL extend feature.
0 DLL extended range
1 Standard (non-extended) range
PCI output hold delay value relative to the PCI_SYNC_IN signal. See the
MPC8240 Hardware Specification for the detailed number of nanoseconds
guaranteed for each setting. There are eight sequential settings for this value;
each corresponds to a set increase in hold time:
000 Recommended for 66 MHz PCI bus
001
010
011
100 Recommended for 33 MHz PCI bus
101
110 Default if reset configuration pins left unconnected
111
The initial values of bits 6 and 5 are determined by the MCP and CKE reset
configuration signals, respectively. See Section 2.4, "Configuration Signals
Sampled at Reset," for more information. As these two pins have internal
pull-up resistors, the default value after reset is 0b110.
0 Reserved
0 PLL sampling when waking from sleep mode
0 The MPC8240 does not sample the PLL configuration pins
1 The MPC8240 samples the PLL configuration pins
0 Reserved
0 0 The MCP output is always driven (asserted if there is an error to report;
negated otherwise) by the MPC8420.
1 The MCP output signal is tri-stated when there is no error to report by the
MPC8240.
Chapter 4. Configuration Registers
0 0
4 3 2 1 0
Description
Reserved
PLL_SLEEP
SHARED_MCP
4-19