Pci Interface Overview - Motorola MPC8240 User Manual

Chapter 7
PCI Bus Interface
The MPC8240's PCI interface complies with the PCI Local Bus Specification , rev 2.1. It is
beyond the scope of this manual to document the intricacies of the PCI bus. This chapter
provides a rudimentary description of the PCI bus operations. The specific emphasis is
directed at how the MPC8240 implements the PCI bus. Designers of systems incorporating
PCI devices should refer to the PCI Local Bus Specification , rev 2.1 for a thorough
description of the PCI local bus.
Much of the available PCI literature refers to a 16-bit quantity
as a word and a 32-bit quantity as a double word. Since this is
inconsistent with the terminology in this manual, the terms
'word' and 'double word' are not used in this chapter. Instead,
the number of bits or bytes indicates the exact quantity.

7.1 PCI Interface Overview

The PCI interface connects the processor core and local memory to the PCI bus to which
I/O components are connected. The PCI bus uses a 32-bit multiplexed, address/data bus,
plus various control and error signals. The PCI interface supports address and data parity
with error checking and reporting. Internal buffers are provided for operations between the
PCI bus and the processor core or local memory. Processor read and write operations each
have a 32-byte buffer, and memory operations have two 32-byte read buffers, and two
32-byte write buffers. Additionally, PCI accesses to local memory must share access to the
processor/memory data bus with other MPC8240 resources (for example, the DMA
controller). See Chapter 12, "Central Control Unit," for more information on both the
internal read and write buffers and the arbitration priorities for the shared
processor/memory data bus.
The PCI interface of the MPC8240 functions both as a master (initiator) and a target device.
Internally, the PCI interface of the MPC8240 is controlled by two state machines (one for
master and one for target operation) running independently of each other. This allows the
MPC8240 to handle two separate PCI transactions simultaneously. For example, if the
MPC8240, as an initiator, is trying to run a burst-write to a PCI device, it may get
disconnected before finishing the transaction. If another PCI device is granted the PCI bus
and requests a burst-read from local memory, the MPC8240, as a target, can accept the
burst-read transfer. When the MPC8240 is granted mastership of the PCI bus, the
burst-write transaction continues.
NOTE:
Chapter 7. PCI Bus Interface 7-1