Pci/Local Memory Buffers - Motorola MPC8240 User Manual

Internal Buffers
previously latched data. Store gathering is only used for writes to PCI memory space not
for writes to PCI I/O space. The store gathering continues until the buffer is scheduled to
be flushed or until the processor issues a synchronizing transaction.
For example, if both PRPWBs are empty and the processor issues a single-beat write to
PCI, the data is latched in the first buffer and the PCI interface of the MPC8240 requests
mastership of the PCI bus for the transfer. The data for the next processor-to-PCI write
transaction is latched in the second buffer, even if the second transaction's address falls
within the same half cache line as the first transaction. While the PCI interface is busy with
the first transfer, any sequential processor single-beat writes within the same half cache line
as the second transfer are gathered in the second buffer until the PCI bus becomes available.

12.1.3 PCI/Local Memory Buffers

There are four data buffers for PCI accesses to local memory—two 32-byte PCI-to-local
memory read buffers (PCMRBs) for PCI reads from local memory and two 32-byte
PCI-to-local memory write buffers (PCMWBs) for PCI writes to local memory.
Figure 12-4 shows the address and data buffers between the PCI bus and the local memory.
Processor Address/Control
PCI/Memory
Write Buffers
(PCMWBs)
Note that many PCI accesses to local memory are snooped on the peripheral logic bus to
ensure coherency between the PCI bus, local memory, and the L1 cache of the processor.
All snoops for PCI accesses to local memory are performed strictly in order.
12-6
Memory Row/Column Address
A D0 D1 D2 D3
A D0 D1 D2 D3
PCI Address/Data
Figure 12-4. PCI/Local Memory Buffers
MPC8240 Integrated Processor User's Manual
Processor/Memory Data
A D0 D1 D2 D3
PCI/Memory
Read Buffers
A D0 D1 D2 D3
(PCMRBs)