Pci Transactions During Nap Mode - Motorola MPC8240 User Manual

Peripheral Logic Power Management
When the peripheral logic is in the nap mode, a PCI transaction referenced to the system
memory, a processor bus request, the assertion of NMI (provided PICR1[MCP_EN] = 1),
the assertion of int from the EPIC unit (due to an interrupt condition into the EPIC unit), or
a hard reset brings the peripheral logic out of the nap mode and into the full-power state.
If the peripheral logic is awakened by any of these causes except for a PCI transaction, the
transaction is serviced, QACK negates (causing the processor core to wake up), and
PMCR1[PM] is cleared preventing the peripheral logic from automatically re-entering the
nap state.

14.3.2.3.1 PCI Transactions During Nap Mode

When the peripheral logic is awakened from the nap state by a PCI-agent initiated
transaction, the transaction is serviced, PMCR1[PM] remains set, QACK negates and the
peripheral logic goes back to the nap state after the transaction has been serviced.
Note that if the MPC8240 is temporarily awakened to service a PCI transaction, the
processor core does not respond to any snoop cycles. Software should, therefore, flush the
L1 cache before allowing the peripheral logic to enter the nap mode if the system allows
PCI accesses to wake up the peripheral logic without guaranteeing that the processor will
snoop incoming PCI transactions.
14.3.2.3.2 PLL Operation During Nap Mode
In peripheral logic nap mode, the PLL is fully operational and locked to PCI_SYNC_IN.
The transition to the full-power state occurs within four processor clock cycles.
14.3.2.4 Peripheral Logic Sleep Mode
Peripheral logic sleep mode provides further power saving compared to the nap mode. As
with nap mode, the peripheral logic does not enter the sleep mode unless the processor core
has requested to enter either nap or sleep mode. The sleep mode is entered when
PMCR1[SLEEP] and PMCR1[PM] are set and the processor core is ready to nap or sleep.
When this occurs, the peripheral logic responds by entering the sleep mode and asserting
the QACK output. It is important to guarantee that no new PCI transactions occur before
PMCR1 is programmed for sleep mode because PCI transactions are not serviced in
peripheral logic sleep mode.
When the peripheral logic is in sleep mode, the only functional units operating are the
on-chip PCI bus arbiter, system RAM refreshing logic (enabled by PMCR1[LP_REF_EN]
for sleep mode), processor bus request monitoring, NMI signal monitoring, the EPIC unit,
2
and the I C unit. All other units are shut down.
Similar to nap mode, the following conditions bring the peripheral logic out of the sleep
mode and into the full-power state: a processor bus request, the assertion of NMI (provided
PICR1[MCP_EN] = 1), the assertion of int from the EPIC unit (due to an interrupt
condition into the EPIC unit), or a hard reset. PMCR1[PM] is always cleared after the core
logic is awakened from the sleep state.
14-10 MPC8240 Integrated Processor User's Manual