Processor Power Management Modes—Details - Motorola MPC8240 User Manual

Processor Core Power Management
14.2.3 Processor Power Management Modes—Details
The following sections describe the characteristics of the MPC8240 power management
modes, the requirements for entering and exiting the various modes, and the system
capabilities provided by the processor core while the power management modes are active.
For the processor to enter nap or sleep mode, the software first programs the processor for
one of those modes. Then the peripheral logic must be programmed for nap or sleep mode.
When the peripheral logic is ready to nap or sleep, it signals that the processor can enter the
nap or sleep mode and asserts the QACK output signal. If the peripheral logic wakes from
nap or sleep (causing QACK to negate), the processor also wakes from nap or sleep mode.
14.2.3.1 Full-Power Mode with DPM Disabled
Full-power mode with DPM disabled power mode is selected when the DPM enable bit
(bit 11) in HID0 is cleared. The following characteristics apply:
• Default state following assertion of HRST_CPU and HRST_CTRL
• All functional units are operating at full processor speed at all times
14.2.3.2 Full-Power Mode with DPM Enabled
Full-power mode with DPM enabled (HID0[11] = 1) provides on-chip power management
without affecting the functionality or performance of the MPC8240 as follows:
• Required functional units are operating at full processor speed
• Functional units are clocked only when needed
• No software or hardware intervention required after mode is set
• Software/hardware and performance transparent
14.2.3.3 Processor Doze Mode
Doze mode disables most functional units but maintains cache coherency by enabling bus
snooping. A snoop hit causes the processor core to enable the data cache, copy the data back
to memory, disable the cache, and fully return to the doze state.
Doze mode is characterized by the following features:
• Most functional units disabled
• Bus snooping and time base/decrementer still enabled
• PLL running and locked to the internal sys_logic_clk signal
To enter the doze mode, the following conditions must occur:
• Set doze bit (HID0[8] = 1).
• The MPC8240 enters doze mode after several processor clocks.
14-4 MPC8240 Integrated Processor User's Manual