Memory Select Error - Motorola MPC8240 User Manual

Error Reporting

13.3.2.3 Memory Select Error

A memory select error occurs when the address for a local memory transaction falls outside
of the programmed boundaries of physical memory. When a memory select error occurs,
ErrDR1[5] is set. If a write transaction causes a memory select error, the write data is
simply ignored. If a read transaction causes the memory select error, the MPC8240 returns
all 1s (0xFFFF_FFFF). No RAS/CS signals are asserted in either case.
13.3.2.4 Memory Refresh Overflow Error
When there are no refresh transactions for a period equal to 16 refresh cycles, the MPC8240
reports the error as a refresh overflow. When the MPC8240 detects a refresh overflow,
ErrDR1[3] is set. See Section 6.2.12, "SDRAM Refresh," and Section 6.3.10,
"FPM or EDO DRAM Refresh," for more information about memory refresh.
13.3.3 PCI Interface Errors
The MPC8240 supports the error detection and reporting mechanism as specified in the PCI
Local Bus Specification, Revision 2.1. The MPC8240 keeps error information and sets the
appropriate error flags when a PCI error occurs (provided the corresponding enable bit is
set), independent of whether the PCI command register is programmed to respond to or
detect the specific error.
In cases of PCI errors, ErrDR1[3] is set to indicate that the error is due to a PCI transaction.
In most cases, ErrDR2[7] is cleared to indicate that the error address in the processor/PCI
error address register is valid. In these cases, the error address is the address as seen by the
PCI bus, not the processor core's physical address.
If NMI is asserted, the MPC8240 cannot provide the error address and the corresponding
bus error status. In such cases, ErrDR2[7] is set to indicate that the error address in the
processor/PCI error address register is not valid.
13.3.3.1 PCI Address Parity Error
Bit 6 of the PCI command register controls whether the MPC8240takes action when it
detects an address or data parity error has occurred. When the MPC8240 detects an address
or data parity error, it sets bit 15 in the PCI status register, regardless of the settings in the
PCI command register. Bit 7 of ErrEnR2 enables the reporting of PCI address parity errors
to the processor core (via mcp, if enabled).
Bit 8 of the PCI command register controls whether the MPC8240 asserts SERR upon
detecting any PCI system error including an address parity error. Whenever the MPC8240
asserts SERR to report a system error on the PCI bus, bit 14 of the PCI status register is set.
Bit 7 of ErrEnR1 enables the reporting (via mcp, if enabled) of SERR assertion by an
external agent on the PCI bus. If ErrEnR1[7] = 1 and the MPC8240 is acting as the initiator
and an external PCI agent asserts SERR two clock cycles after the address phase, the error
is recorded in bit 7 of ErrDR1 and a machine check is generated to the processor core.
Chapter 13. Error Handling 13-9