System Memory Refresh During Sleep Mode - Motorola MPC8240 User Manual

Example Code Sequence for Entering Processor and Peripheral Logic Sleep Modes
Note that the PLL_CFG[0:4] pins are sampled when the MPC8240 is waking from sleep
mode only if PMCR2[SLEEP] = 1.

14.3.2.4.1 System Memory Refresh during Sleep Mode

When the peripheral logic is in sleep mode, the system memory contents can be maintained
either by enabling the memory's self-refresh mode or by having the operating system copy
all the memory contents to the hard disk before the peripheral logic enters the sleep state.
Alternatively, the MPC8240 refresh logic can continue to perform the refresh function in
sleep mode if PMCR1[LP_REF_EN] is set. In this case, MCCR1[SREN] is used to
determine whether the refresh is a self refresh (SREN = 1) or a CBR refresh (SREN = 0).
If LP_REF_EN is cleared, the refresh operations stop when the MPC8240 enters the sleep
mode.
When the MPC8240 is in the sleep state using CBR refresh and keeping the PLL in locked
operation, the wake-up latency is comparable to that of nap mode (within four processor
clock cycles). However, additional wake-up latency is incurred if the system uses the
self-refresh mode and/or turns off the PLL during the sleep state.
14.3.2.4.2 Disabling the PLL during Sleep Mode
When the peripheral logic is in sleep mode, the PLL for the peripheral logic block and the
PCI_SYNC_IN input may be disabled by an external power-management controller (PMC)
for further power saving. The PLL can be disabled by setting the PLL_CFG(0:4) pins to the
PLL bypass mode. See the MPC8240 Hardware Specification for detailed information on
the PLL modes. Disabling the PLL and/or the PCI_SYNC_IN input during sleep mode
should not occur until after the assertion of the QACK output ensuring that the processor is
in either nap or sleep mode.
If the peripheral logic PLL is disabled, the external PMC chip should trap all the wake-up
events so that it can turn on the PLL (to guarantee the relock time) and/or the
PCI_SYNC_IN input before forwarding the wake-up event to the MPC8240. When
recovering from sleep mode, the external PMC has to re-enable the PLL and
PCI_SYNC_IN first, and then wake up the MPC8240 (using any of the wake-up methods)
after 100 µs of PLL relock time.
14.3.2.4.3 SDRAM Paging during Sleep Mode
SDRAM systems that have paging mode enabled must disable paging mode before entering
the sleep mode, to avoid memory loss and corruption. After the peripheral logic exits the
sleep mode and returns to the full-power state, paging mode can once again be enabled.
14.4 Example Code Sequence for Entering Processor
and Peripheral Logic Sleep Modes
The following is a sample code sequence for putting the processor core and peripheral logic
into sleep mode. Note that there are no-op instructions used to make the code read and
Chapter 14. Power Management 14-11