Memory Interface Signal Summary - Motorola MPC8240 User Manual

Memory Clock
Data path
PCI
32-bit
Bus
PCI Bus
Interface
Interface logic
DMA 1 DMA 0
Queue Queue
64 bytes
PCI
Clock-In
Figure 6-1. Block Diagram for Memory Interface

6.1 Memory Interface Signal Summary

Table 6-1 summarizes the memory interface signals. Note that some signals function
differently depending on the type of memory system the MPC8240 is configured to support.
Signal Name
RAS[0:7]
CAS[0:7]
CS[0:7]
DQM[0:7]
WE
Processor
PLL
32- or 64-bit
Data Bus
Central
Control
Unit
SDRAM
Configuration
Registers
FPM/EDO
DRAM
Processor
PLL
Peripheral
Memory Clock
Logic
PLL
Table 6-1. Memory Interface Signal Summary
Signal Name
DRAM row address strobe 0–7
DRAM column address strobe 0–7
SDRAM chip select 0–7
SDRAM data mask in/out 0–7
Write enable
Chapter 6. MPC8240 Memory Interface
Memory Interface Signal Summary
Processor
Core
Peripheral
Logic Bus
32-bit
Address Bus
Parity
RMW Parity
64-bit ECC
Parity
RMW Parity
Controller
64-bit ECC
Interface
ROM/Flash
Port X
64-bit
ROM/Flash
Port X
8-bit
ECC or Parity
Data path
64-bit In-Line ECC
Error Injection/
Capture
Memory Control
DLL
Alternate Function
CS[0:7]
DQM[0:7]
RAS[0:7]
CAS[0:7]
—
SDBA[1:0]
SDMA[12:0]
Address
Path AR[19:12]
SDRAS
SDCAS
CKE
WE
PAR[0:7]
Memory
RAS/CS[0:7]
CAS/DQM[0:7]
FOE
RCS0
RCS1
AS
MDH[0:31]
MDL[0:31]
SDRAM_SYNC_IN
SDRAM_SYNC_OUT
SDRAM _CLK[0:3]
Pins I/O
8 O
8 O
8 O
8 O
1 O
6-3