Dma Chaining Mode - Motorola MPC8240 User Manual

In direct mode, the DMA controller has the ability to hold the destination address or the
source address to a fixed value for every transfer. When the DAHE bit is set, the destination
address is held, and the DAHTS bit indicates the size used for the transfer. When the SAHE
bit is set, the source address is held and the SAHTS bit indicates the size used for transfer.
Note that PCI reads from local memory always check the PCI-to-system memory read
buffers (PCMRB) for an address hit. If there is an address match, the data is read directly
from the buffer instead of local memory. Because the DMA controller functions as a PCI
device on the MPC8240 this address checking also occurs for DMA reads from local
memory. Thus, when SAHE is set, DMA transfers from local memory (local-to-local or
local-to-PCI) check the PCMRBs for a hit on every transfer. In this case, after the first read
from memory, one of the PCMRBs will result in a hit on-chip, and the same data is read
from the PCMRB every time (the access is not performed to memory). Thus, if data at the
actual source address is changing, the DMA controller does not read the changed data.
Refer to Section 12.1.3, "PCI/Local Memory Buffers," for more information about the
PCMRBs.
Only one of DAHE or SAHE may be set at one time. These bits are described in Table 8-3.

8.3.2 DMA Chaining Mode

In chaining mode, the DMA controller loads descriptors from memory prior to a DMA
transfer. The DMA controller begins the transfer according to the descriptor information
loaded for the segment. Once the current segment is finished, the DMA controller reads the
next descriptor from memory and begins another DMA transfer. The process is finished if
the current descriptor is the last one in memory, or an error condition has occurred.
DMA chaining mode can be used to implement scatter gathering. In scatter gathering with
the MPC8240, a group of descriptors can transfer (scatter) data from a contiguous space of
memory to a non-contiguous destination or, likewise, data from a non-contiguous
destination can be gathered to a contiguous region of memory.
Source and destination address hold is not supported in
chaining mode.
8.3.2.1 Basic Chaining Mode Initialization
The initialization steps for a DMA transfer in chaining mode are as follows:
1. Build descriptor segments in memory. Refer to the Section 8.6, "DMA Descriptors
for Chaining Mode," for more information.
2. Poll the CB bit in the DSR to make sure the DMA channel is idle.
3. Initialize the CDAR to point to the first descriptor in memory.
4. Initialize the CTM bit in the DMR to indicate chaining mode. Other control
parameters in the DMR can also be initialized here if necessary.
5. Clear and then set the CS bit in the DMR to start the DMA transfer.
NOTE:
Chapter 8. DMA Controller
DMA Operation
8-5