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the memory data path but also to correct single-bit errors in the 64-bit data path. The ECC
logic in the MPC8240 detects and corrects all single-bit errors and detects all double-bit
errors and all errors within a nibble. Other errors may be detected but are not guaranteed to
be either detected or corrected. Multiple-bit errors are always reported when detected.
However, when a single-bit error occurs, the single-bit error counter register is
incremented, and its value is compared to the single-bit error trigger register. If the values
are not equal, no error is reported; if the values are equal, then an error is reported. Thus,
the single-bit error registers may be programmed so that minor faults with memory are
corrected and ignored, but a catastrophic memory failure generates an interrupt. The
syndrome equations for the ECC code are shown in Table 6-23 and Table 6-24. For
supported configurations, see Table 6-17.
.
Table 6-23. The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 0:31)
Syndrome
Bit
0 1 2 3 4 5 6 7 8 9
0
x x x x x x x x x x x x x x x x
1
x
2
x
3
x
4
5
6
7
x x x x
Table 6-24. The MPC8240 FPM or EDO ECC Syndrome Encoding (Data bits 32:63)
Syndrome
3
3
3
Bit
2
3
4
0
x
1
2
x x x x x x x x x x x x x x x x
3
x
4
x x x
5
6
7
x x
1
1
0
1
x
x
x
x
x
x
x
x
x
x x x x
x x x x x x x x
3
3
3
3
3
4
4
4
4
5
6
7
8
9
0
1
2
3
x
x
x
x
x
x
x
x x x
x x x
x x x x
x x x x x x x x x x x x
x x
x x x x
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
Data Bit
1
1
1
1
1
1
1
1
2
2
3
4
5
6
7
8
9
0
x
x
x x x x x x x x x x x x x x x x
x
x
x
x
x
x
x x
x x x x
x x x x
x x x x x x x
Data Bit
4
4
4
4
4
4
5
5
5
4
5
6
7
8
9
0
1
2
x
x
x x
x
x
x
x
x x x
x x x x x x x x x x x x
x x x x x x x x
2
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
9
x
x
x
x
x
x
x
x x
x x
x x x x
x x x x x x x x
x
x x x x
5
5
5
5
5
5
5
6
6
3
4
5
6
7
8
9
0
1
x
x
x
x
x
x
x
x
x x x x
x x x x
x x x x x x x x
x x x
3
3
0
1
x
x x
6
6
2
3
x
x
6-63
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