Motorola MPC8240 User Manual page 298

ROM/Flash Interface Operation
ROMFAL and ROMNAL are configured to their maximum value at reset in order to
accommodate initial boot code fetches. The MCCR1[BURST] configuration bit is cleared
at reset. ROM interface timing configuration, and use of the ROMFAL and ROMNAL
parameters, are shown in Figure 6-55, Figure 6-56, and Figure 6-57.
MCLK
A[0:1]
A[2:19]
FOE, RCSn
DATA
3 cycles
(constant)
Data sampled
Figure 6-55. Read Access Timing for Non-Burst ROM/Flash Devices in
MCLK
A[0:1]
A[2:19]
FOE, RCSn
DATA
3 cycles
(constant)
Data sampled
Figure 6-56. Read Access Timing (Cache Block) for Burst ROM/Flash Devices
6-80
D0
ROMFAL 3 cycles
(constant)
ROMFAL (ROM first access latency) = 3–34 clocks
MCCR1[BURST] = 0 (default value at reset)
32- or 64-Bit Mode
D0
ROMFAL ROMNAL
2 cycles 2 cycles
(constant) (constant)
ROMFAL (ROM first access latency) = 3–34 clocks
ROMNAL (ROM nibble access latency) = 0–9 clocks
MCCR1[BURST] = 1
in 64-Bit Mode
MPC8240 Integrated Processor User's Manual
ROMFAL 3 cycles
(constant)
D1 D2
ROMNAL ROMNAL
2 cycles
(constant)
D1 D2
ROMFAL
D3
3 cycles
(constant)