Programming Guidelines - Motorola MPC8240 User Manual

2
10.3.5 I C Data Register (I2CDR)
The data register is shown in Figure 10-7.
31
Table 10-8 describes I2CDR.
Table 10-8. I2CDR Field Descriptions—Offset 0x0_3010
Reset
Bits Name
Value
31–8 —
7–0 DATA 0x00

10.4 Programming Guidelines

This section describes some programming guidelines recommended for the I
on the MPC8240. Also included is a recommended flowchart for the I
routines.
2
The I C registers in this chapter are shown in little-endian format. If the system is in
big-endian mode, software must swap the bytes appropriately. Also, a sync assembly
instruction should be executed after each I
in-order execution.
The MPC8240 does not guarantee it will recover from all illegal I
addition, a malfunctioning device may hold the bus captive. A good programming practice
is for software to rely on a watchdog timer to help recover from I
routine should also handle the case when the status bits returned after an interrupt are not
consistent with what was expected due to illegal I
2
Example I C code can be found in the MPC8240 Device Driver Toolbox available through
the PowerPC web site: www.mot.com/SPS/PowerPC/teksupport/faqsolutions/code (using
the 'code samples' link for the Dink drivers directory).
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
Figure 10-7. I C Data Register (I2CDR)
R/W
R Reserved
R/W Transmission starts when a 7-bit address is written to bits 7–1 of this field, the R/W
bit (I2CCR[MTX]) is set, and the I
initiated when data is written to the I2CDR. The most significant bit (msb) is sent
first in both cases. In the master receive mode, reading the data register allows the
read to occur but also initiates next byte data receiving. In slave mode, the same
function is available after it is addressed.
Chapter 10. I
Description
2
C interface is the master. A data transfer is
2
C register read/write access to guarantee
2
C bus hangs. The recovery
2
C bus protocol behavior.
2
C Interface
Programming Guidelines
Reserved
Data
8 7 0
2
C interface
2
C interrupt service
2
C bus activity. In
10-13