Motorola MPC8240 User Manual page 37

Integrated host processor with integrated pci
Table of Contents

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Table
Number
D-46
PowerPC Instruction Set Legend ............................................................................... D-38
E-1
Bit Settings for CR0 Field of CR..................................................................................E-4
E-2
Bit Settings for CR1 Field of CR..................................................................................E-5
E-3
CRn Field Bit Settings for Compare Instructions .........................................................E-5
E-4
FPSCR Bit Settings.......................................................................................................E-6
E-5
Floating-Point Result Flags in FPSCR .........................................................................E-8
E-6
XER Bit Definitions......................................................................................................E-8
E-7
BO Operand Encodings ...............................................................................................E-9
E-8
MSR Bit Settings ........................................................................................................E-13
E-9
Floating-Point Exception Mode Bits ..........................................................................E-15
E-10
BAT Registers—Field and Bit Descriptions...............................................................E-16
E-11
BAT Area Lengths .....................................................................................................E-17
E-12
SDR1 Bit Settings .......................................................................................................E-17
E-13
Segment Register Bit Settings (T = 0) ........................................................................E-18
E-14
Conventional Uses of SPRG0–SPRG3.......................................................................E-18
E-15
External Access Register (EAR) Bit Settings.............................................................E-20
E-16
DCMP and ICMP Bit Settings....................................................................................E-21
E-17
HASH1 and HASH2 Bit Settings ...............................................................................E-22
E-18
RPA Bit Settings .........................................................................................................E-23
E-19
Instruction Address Breakpoint Register Bit Settings ................................................E-23
E-20
HID0 Field Descriptions .............................................................................................E-24
E-21
HID0[BCLK] and HID0[ECLK] CKO Signal Configuration ....................................E-27
E-22
HID1 Field Descriptions .............................................................................................E-27
E-23
HID2 Field Descriptions .............................................................................................E-28
TABLES
Title
Tables
Page
Number
xxxvii

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