Configuration Register Access In Big-Endian Mode - Motorola MPC8240 User Manual

Code sequence: stw
sync
stb
sync
Results:Address 0xFEC0_0000 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xFFDD_FFFF (AB to A8)
Example: Map A configuration sequence, 4-byte data write to register at address offset
0xA8
Initial values:r0 contains 0x8000_00A8
r1 contains 0x8000_0CF8
r2 contains 0xAABB_CCDD
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stw
sync
stw
sync
Results:Address 0x8000_0CF8 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xAABB_CCDD (AB to A8)
Example: Map A configuration sequence, 2-byte data write to register at address offset
0xAA. (Note that in this example, the value 0x8000_00A8 is the configuration address
register, not 0x8000_00AA. The address offset 0xAA is generated by using 0x8000_0CFE
for the data access.)
Initial values:r0 contains 0x8000_00A8
r1 contains 0x8000_0CF8
r2 contains 0xAABB_CCDD
Register at 0xA8 contains 0xFFFF_FFFF (AB to A8)
Code sequence: stw
sync
sth
sync
Results:Address 0x8000_0CF8 contains 0x8000_00A8 (MSB to LSB)
Register at 0xA8 contains 0xCCDD_FFFF (AB to A8)
Example: Map A configuration sequence, 1-byte data read from register at address
offset 0xA9
Initial values:r0 contains 0x8000_00A8
r1 contains 0x8000_0CF8
Register at 0xA8 contains 0xAABB_CCDD (AB to A8)
Code sequence: stw
sync
lbz
sync
Results:Address 0x8000_0CF8 contains 0x8000_00A8 (MSB to LSB)
r2 contains 0x0000_00CC
4.1.2 Configuration Register Access in Big-Endian Mode
When the processor and peripheral logic are in big-endian mode, software must either use
the load/store with byte reversed instructions (lhbrx, lwbrx, sthbrx, and stwbrx) or
r0,0(r1)
r3,2(r2)
r0,0(r1)
r2,4(r1)
r0,0(r1)
r2,6(r1)
r0,0(r1)
r2,5(r1)
Chapter 4. Configuration Registers
Configuration Register Access
4-3