Peripheral Logic Overview; Peripheral Logic Features - Motorola MPC8240 User Manual

1.4 Peripheral Logic Overview

The peripheral logic block integrates a PCI bridge, memory controller, DMA controller,
EPIC interrupt controller/timers, a message unit with an Intelligent Input/Output (I
message controller, and an Inter-Integrated Circuit (I
the overall packaging requirements and the number of discrete devices required for an
embedded system.
Figure 1-6 shows the major functional units within the peripheral logic block. Note that this
is a conceptual block diagram intended to show the basic features rather than an attempt to
show how these features are physically implemented.
Peripheral Logic Block
Message
Unit
(with I
DMA
Controller
2
I
2
I C
Controller
5 IRQs/
EPIC
16 Serial
Interrupt
Interrupts
Controller
/Timers
Figure 1-6. MPC8240 Peripheral Logic Block Diagram

1.4.1 Peripheral Logic Features

Major features of the peripheral logic are as follows:
• Peripheral logic bus
— Supports various operating frequencies and bus divider ratios
— 32-bit address bus, 64-bit data bus
— Supports full memory coherency
Data (64-Bit)
Address
(32-Bit)
O)
2
Central
Control
Unit
C
PCI Bus
Interface Unit
Address
Translator Arbiter
32-Bit
PCI Interface
Chapter 1. Overview
2
C) controller. The integration reduces
Peripheral Logic
Bus
Data Path
ECC Controller
Memory
Controller
Configuration
Registers
DLL
Peripheral Logic
PLL
PCI
Fanout
Buffers
OSC_IN
Five
Request/Grant
Pairs
Peripheral Logic Overview
Data Bus
(32- or 64-bit)
with 8-bit Parity
or ECC
Memory/ROM/
Port X Control/Address
SDRAM_SYNC_IN
SDRAM Clocks
PCI_SYNC_IN
PCI Bus
Clocks
1-11
O)
2