Pci Parity - Motorola MPC8240 User Manual

7.6.1 PCI Parity

Generating parity is not optional; it must be performed by all PCI-compliant devices. All
PCI transactions, regardless of type, calculate even parity; that is, the number of 1s on the
AD[31:0], C/BE[3:0], and PAR signals all sum to an even number.
Parity provides a way to determine, on each transaction, if the initiator successfully
addressed the target and transferred valid data. The C/BE[3:0] signals are included in the
parity calculation to ensure that the correct bus command is performed (during the address
phase) and correct data is transferred (during the data phase). The agent responsible for
driving the bus must also drive even parity on the PAR signal one clock cycle after a valid
address phase or valid data transfer, as shown in Figure 7-11.
PCI_SYNC_IN
AD[0:31]
C/BE[0:3]
PAR
FRAME
IRDY
DEVSEL
TRDY
PERR
SERR
During the address and data phases, parity covers all 32 address/data signals and the four
command/byte enable signals regardless of whether all lines carry meaningful information.
Byte lanes not actually transferring data must contain stable (albeit meaningless) data and
are included in
interrupt-acknowledge commands, some address lines are not defined but are driven to
stable values and are included in parity calculation.
Agents that support parity checking must set the detected parity error bit in the PCI status
register when a parity error is detected. Any additional response to a parity error is
controlled by the parity error response bit in the PCI command register. If the parity error
response bit is cleared, the agent ignores all parity errors.
ADDR DATA
CMD Byte enables
Figure 7-11. PCI Parity Operation
parity calculation.
Chapter 7. PCI Bus Interface
ADDR DATA
CMD Byte enables
During configuration,
PCI Error Functions
special-cycle, or
7-31