Mbyte Rom System Including Parity Paths To Dram—64-Bit Mode - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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ROM/Flash Interface Operation
MDH[0:31]
MDL[0:31]
PAR[0:7]
SDMA[12:0]
SDBA[0]
Buffers
RCS[0]
RCS[1]
MPC8240
Address
Signals
(Outputs)
Logical Names
Notes:
1.
The array of ROM memory devices are 8-Mbit (1M x 8 or 512K x 16) configured for 1M x 8 operation.
2.
A[-1] is the lsb of the ROM memory devices.
3.
BHE connected to GND enables A[-1] as an input and sets Q[15:8] to Hi-Z.
4.
Q[7:0] of the ROM Memory devices are data outputs connected to MDH[0-31] and MDL[0:31].
MDH[0:7] is the most significant byte lane and MDL[24:31] is the least significant byte lane.
5.
All OE and BHE signals are connected to GND.
6.
RCS0 is connected to all CE in Bank 0 (8 Mbytes) and RCS1 is connected to all CE in Bank 1 (8 Mbytes).
Figure 6-50. 16-Mbyte ROM System Including Parity Paths to DRAM—64-Bit Mode
6-74
Data Path to/from DRAM/SDRAM Array
Parity Path to/from DRAM/SDRAM Array
Address Path to DRAM/SDRAM Array
1Mx8 ROM
2Mx8 SDRAM
A[0:18]
2Mx8 SDRAM
A[-1]
A[0-11]
2Mx8 SDRAM
BA[0-1]
A(11-0)
Q[15:8]
RAS
2Mx8 SDRAM
BA(1-0)
A(11-0)
Q[7:0]
CAS
RAS
2Mx8 SDRAM
BA(1-0)
A[0-11]
WE
DQ[0-7]
CAS
RAS
2Mx8 SDRAM
CE
BA[0-1]
A[0-11]
CKE
WE
DQ(7-0)
CAS
RAS
2Mx8 SDRAM
BA[0-1]
OE
A[0-11]
CLK
CKE
WE
DQ(7-0)
CAS
RAS
BA[0-1]
BHE
A[0-11]
CS
CLK
CKE
WE
DQ[0-7]
CAS
RAS
BA[0-1]
BHE
CS
CLK
CKE
WE
DQ[0-7]
CAS
RAS
GND
BHE
CS
CLK
CKE
WE
DQ[0-7]
CAS
BHE
CS
CLK
CKE
WE
DQ[0-7]
BHE
CS
CLK
CKE
BHE
CS
CLK
BHE
CS
BHE
PAR
0
1
2
3
4
5
6
msb
1
1
1
1
1
1
1
9
8
7
6
5
4
3
MPC8240 Integrated Processor User's Manual
1Mx8 ROM
2Mx8 SDRAM
A[0:18]
2Mx8 SDRAM
A[-1]
A[0-11]
2Mx8 SDRAM
BA[0-1]
A(11-0)
NC
RAS
2Mx8 SDRAM
BA(1-0)
MDH[0:7]
A(11-0)
CAS
RAS
BA(1-0)
MDH[8:15]
A[0-11]
WE
CAS
RAS
CE
BA[0-1]
MDH[16:23]
CKE
WE
CAS
RAS
OE
MDH[24:31]
CLK
CKE
WE
CAS
MDL[0:7]
BHE
CS
CLK
CKE
WE
MDL[8:15]
BHE
CS
CLK
CKE
MDL[16:23]
GND
BHE
CS
CLK
MDL[24:31]
BHE
CS
BHE
BHE
SDBA
7
0
1
9
8
7
0
AR
1
11
1
9
8
7
2
0
Q[15:8]
NC
MDH[0:7]
Q[7:0]
2Mx8 SDRAM
MDH[8:15]
DQ[0-7]
2Mx8 SDRAM
A[0-11]
MDH[16:23]
DQ(7-0)
2Mx8 SDRAM
BA[0-1]
A[0-11]
MDH[24:31]
DQ(7-0)
RAS
BA[0-1]
A[0-11]
MDL[0:7]
DQ[0-7]
CAS
RAS
BA[0-1]
MDL[8:15]
WE
DQ[0-7]
CAS
RAS
MDL[16:23]
CKE
WE
DQ[0-7]
CAS
MDL[24:31]
CLK
CKE
WE
DQ[0-7]
CS
CLK
CKE
CS
CLK
BHE
CS
BHE
SDMA
6
5
4
3
2
1
lsb
6
5
4
3
2
1
0
0

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