Serial Interrupt Timing Protocol - Motorola MPC8240 User Manual

EPIC Serial Interrupt Interface
Note that initially, interrupt source 0 is sampled at the fifth S_CLK rising edge after S_RST
negates. Also, once S_RST is asserted, it is not asserted again until after an EPIC reset, and
the EPIC unit is subsequently programmed to serial mode again.

11.6.2 Serial Interrupt Timing Protocol

Figure 11.7 shows the relative timing for the serial interrupt interface signals.
MPC8240
EPIC Unit
S_CLK
S_RST
S_FRAME
S_INT
Figure 11-3. Serial Interrupt Interface Protocol
11.6.3 Edge/Level Sensitivity of Serial Interrupts
The interrupt detection is individually programmable for each source to be edge- or
level-sensitive by writing the sense and polarity bits of the vector/priority register of the
particular interrupt source. Refer to Section 11.3.6.1, "Interrupt Pending Register
(IPR)—Non-programmable," and the serial vector/priority register description in
Section 11.9.8.1, "Direct & Serial Interrupt Vector/Priority Registers (IVPRs, SVPRs)," for
more edge/level sensitivity information.
Note that for level-sensitive interrupts there is a potential race condition between an EOI
(end of interrupt) command for a specific interrupt source and the sampling of the same
specific interrupt source as inactive. Level-sensitive interrupts are cleared from an interrupt
priority register only when sampled as inactive; therefore, a second interrupt for the same
source may occur, although the specific interrupt has already been serviced.
Software can avoid this second interrupt by delaying the EOI command to the EPIC unit.
Depending on the interrupt source device being serviced, one possible software method is
to first clear the interrupt from the source before executing any other necessary read or write
transactions to service the interrupt device. In any case, the delay should be no less than 16
serial clocks after clearing the interrupt at the source device.
11-12
S_CLK
S_FRAME
External Logic
S_INT
S_RST
1 2 3 4 5
0 1 2
EPIC starts sampling
serial interrupts here.
MPC8240 Integrated Processor User's Manual
Serial Interrupt
source 0
source 15
3 4 5 6 7 8 9 10 11 12 13
14 15 0 1