Motorola MPC8240 User Manual page 634

little-endian mode
transfers to I/O space, B-12
transfers to memory space, B-9
master-abort transaction termination, 13-10
master-initiated transaction termination, 7-17
memory space addressing, 7-12
MPC107 as PCI bus master, 7-2
MPC107 as PCI target, 7-3
nonmaskable interrupt, 13-11
overview, 1-14, 7-1
PCI address translation, 7-34
PCI attribute signals, 1-20
PCI commands
C/BEn signals, 7-9
command summary, 7-10
encodings, 7-9
interrupt-acknowledge transaction, 7-27
special-cycle command, 7-28
PCI Local Bus Specification, xliii, 4-10
PCI special-cycle operations, 7-28
PCI System Design Guide, xliii
PCI/local memory buffers, 12-6
PCI-to-ISA bridge, 13-5
processor-to-PCI-read buffer (PRPRB), 12-4
processor-to-PCI-write buffers (PRPWBs), 12-5
registers, see Registers, PCI interface, 4-11, 7-22
retry PCI transactions, 7-18
signals, see Signals, PCI interface, 2-13, 7-2
special cycle command, 7-28
special-cycle operations, 7-28
system control
nonmaskable interrupt, 2-27
target-abort error, 7-18, 13-10
target-disconnect, 7-2, 12-4
target-disconnect termination, 7-18
target-initiated termination, 7-18
transaction termination, 7-14
turnaround cycle, 7-14
PCI interface, see Interfaces, PCI interface
PCI_CLK (PCI clock), 2-33
PCI_SYNC_IN (PCI feedback clock), 2-33
PCI_SYNC_OUT (PCI clock synchronize out), 2-33
PCLSR (PCI cache line size) register, 4-14
PCSRBAR (PCSR base address) register, 4-15
PCTPR (processor current task priority)
register, 11-27
Peripheral control and status registers, see EUMB
registers, 3-19
Peripheral logic
block diagram, 1-11
bus interface, 5-9
bus operation, 1-10
features list, 1-11
major functional units, 1-12
Index-10
INDEX
MPC8240 Integrated Processor User's Manual
overview, 1-11
power management modes, 1-18
PERR (PCI parity error) signal, 2-14, 7-32, 13-5
Phase locked loop, 14-5
PI (processor initialization) register, 11-19
PICRs (processor interface configuration registers)
PICR1 register
CF_BREAD_WS bit, 4-29
PICRs (processor interface configuration) registers
PICR1 register
bit settings/overview, 4-29
FLASH_WR_EN bit, 4-30, 13-7
LE_MODE (endian mode) bit, 4-31
MCP_EN bit, 2-27, 13-4
speculative PCI reads bit, 4-31
ST_GATH_EN bit, 4-30
PICR2 register
bit settings/overview, 4-32
CF_APARK bit, 4-31
CF_APHASE_WS bit, 4-33
CF_SNOOP_WS bit, 4-32
FLASH_WR_LOCKOUT bit, 4-32, 13-7
PLL_CFG (PLL configuration) signals, 2-31
PLTR (PCI latency timer) register, 4-14
PMAA (PCI memory address attribute) signals, 2-30
Port X interface
block diagram, 6-90
overview, 6-89
Power management
doze mode, 14-4, 14-9
dynamic power management, 14-2
full-power mode, 14-4
nap mode, 7-28, 14-5, 14-9
overview, 1-18, 14-1
PCI special-cycle operations, 7-28
peripheral logic programmable power
modes, 1-19, 14-8
PMCR registers
overview, 4-17
PMCR, PM bit, 4-18
power mode transition, 14-7
processor core, 14-1
programmable power modes, 1-18, 14-2
sleep mode, 4-17, 14-6, 14-10
software considerations, 14-6
Power management signals, see Signals
Power-on reset
configuration pins sampled, 2-38
intialization at power-on reset (POR), 13-3
output signal state, 2-7
SDRAM initialization, 6-16
PowerPC architecture
instruction list, D-1, D-9, D-17
instruction set, 5-18