SDRAM Interface Operation
6.2.13 Processor-to-SDRAM Transaction Examples
The figures in this section provide examples of signal timing for 60x processor-to-SDRAM
transactions. Figure 6-21 and Figure 6-22 show series of processor burst and single-beat
reads to SDRAM. Figure 6-23 and Figure 6-24 show series of processor burst and
single-beat writes to SDRAM. Figure 6-25 shows a series of processor single-beat reads
followed by writes to SDRAM.
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MPC8240 Integrated Processor User's Manual