A.1 Address Space For Map A - Motorola MPC8240 User Manual

Appendix A
Address Map A
The MPC8240 supports two address maps. The preferred address map, map B, is described
in Chapter 3, "Address Maps." This appendix describes address map A.
Address map A conforms to the now-obsolete PowerPC reference platform (PReP)
specification. Support for address map A is provided solely for backward compatibility
with MPC106-based systems that used the PReP address map. It is strongly recommended
that new designs use map B and existing designs be revised to use map B because map A
may not be supported in future devices.

A.1 Address Space for Map A

The address space of map A is divided into four areas—local memory, PCI I/O, PCI
memory, and system ROM space. Table A-1, Figure A-2, and Table A-3 show separate
views of address map A for the processor core, a PCI memory device, and a PCI I/O device,
respectively. When configured for map A, the MPC8240 translates addresses across the
internal peripheral logic bus and the external PCI bus as shown in Figure A-1 through
Figure A-3.
Processor Core Address Range
Hex
0000_0000 3FFF_FFFF
4000_0000 7FFF_FFFF
8000_0000 807F_FFFF
8080_0000 80FF_FFFF
8100_0000 BF7F_FFFF
BF80_0000 BFFF_FFEF
BFFF_FFF0 BFFF_FFFF
C000_0000 FEFF_FFFF
FF00_0000 FFFF_FFFF
Table A-1. Address Map A—Processor View
Decimal
0 1G - 1
1G 2G - 1
2G 2G + 8M - 1
2G + 8M 2G + 16M - 1
2G + 16M 3G - 8M - 1
3G - 8M 3G - 16 - 1
3G - 16 3G - 1
3G 4G - 16M - 1
4G - 16M 4G - 1
Appendix A. Address Map A
PCI Address Range
No PCI cycle
No PCI cycle
0000_0000–007F_FFFF
0080_0000–00FF_FFFF
0100_0000–3F7F_FFFF
3F80_0000–3FFF_FFEF
3FFF_FFF0–3FFF_FFFF
0000_0000–3EFF_FFFF
4
FF00_0000–FFFF_FFFF
Definition
Local memory space
Reserved
1,2
PCI I/O space
PCI configuration
3
direct access
PCI I/O space
Reserved
PCI interrupt
acknowledge
PCI memory space
4
ROM space
A-1