Column Bit Multiplexing During The Column Phase (Cas) - Motorola MPC8240 User Manual

6.3.2.2 Column Bit Multiplexing During the Column Phase (CAS)

The following list shows the relationships between the internal physical addresses
A[21 –29 ] and the external address pins SDMA[7:0] during the assertion of CAS:
msb lsb
• In the in 32-bit bus mode, SDMA[7:0] contains A[22:29].
• In the 64-bit bus mode, SDMA[7:0] contains A[21:28].
The encoding of SDMA[11:8] during CAS depends on the bus mode selected (32- or
64-bit) and on the number of row bits set in MCCR1 as shown in Table 6-18.
Table 6-18. SDMA[11:8] Encodings for 32- and 64-Bit Bus Modes
6.3.2.3 Graphical View of the Row and Column Bit Multiplexing
Figure 6-32 and Figure 6-33 provide a graphical view of the row and column bit
multiplexing.
Row Bits 32-Bit Bus Mode
9 A[9:11, 21]
10 A[8:10, 21]
11 A[7:9, 21]
12 A[6:8, 21]
13 A[unused, 7:8, 21]
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
64-Bit Bus Mode
A[8:11]
A[7:10]
A[6:9]
A[5:8]
A[unused, 6:8]
6-51