Destination Address Registers (Dars) - Motorola MPC8240 User Manual

Figure 8-7 shows the bits in the SARs.
31
Table 8-4 describes the bit settings for the SARs.
Table 8-6. SAR Field Description—Offsets 0x110, 0x210
Reset
Bits Name
Value
31–0 SAR All 0s

8.7.5 Destination Address Registers (DARs)

The DARs indicate the address to which the DMA controller writes data. This address can
be either a PCI memory or local memory address. The software has to ensure that this is a
valid memory address. In agent mode, all DMA to PCI write transactions are translated if
the DAR address is within the outbound translation window. See Section 3.3.2, "Outbound
PCI Address Translation," for more information.
Figure 8-8 shows the bits in the SARs.
31
Figure 8-8. Destination Address Register (DAR)
Table 8-4 describes the bit settings for the DARs.
Table 8-7. DAR Field Description—Offsets 0x118, 0x218
Reset
Bits Name R/W
Value
31–0 DAR All 0s RW
8.7.6 Byte Count Registers (BCRs)
The BCRs contain the number of bytes per transfer. The maximum transfer size is 64
Mbytes - 1 byte.
Figure 8-7. Source Address Register (SAR)
R/W
RW Source address. This register contains the source address of the DMA transfer. The
content is updated by the MPC8240 after every DMA read operation.
Destination address. This register contains the destination address of the DMA
transfer. The content is updated by the MPC8240 after every DMA write operation.
Chapter 8. DMA Controller
SAR
Description
DAR
Description
DMA Register Descriptions
0
0
8-21