Motorola MPC8240 User Manual page 540

sync
sthbrx r4, 0, r6
sync
addis r3,r0,BMC_BASE
ori r3,r3,0x0006
stwbrx r3,0,r5
sync
li r3, 0x0002
lhbrx r4, r3, r6
sync
ori r4, r4, 0xffff
sthbrx r4, r3, r6
//-------PICR1
addis r3,r0,BMC_BASE
ori r3,r3,PROCINTCONF1
stwbrx r3,0,r5
sync
lwbrx r4,0,r6
lis r0,0x0011
ori r0,r0,0x0000
and r4,r4,r0
lis r0,0xff00
oris r0, r0, 0x0000
oris r0, r0, 0x0004
ori r0, r0, 0x1000
ori r0, r0, 0x0800
ori r0, r0, 0x0200
ori r0, r0, 0x0008
or r4, r4, r0
stwbrx r4,0,r6
//-------PICR2
addis r3,r0,BMC_BASE// Set PICR2 (AC)
ori r3,r3,PROCINTCONF2
stwbrx r3,0,r5
sync
lwbrx r4,0,r6
lis r0, 0xfff3
ori r0, r0, 0xfff3
and r4, r4, r0
lis r0, 0x0000
oris r0, r0, 0x0400
// oris r0, r0, 0x0004
oris r0, r0, 0x0000
// ori r0, r0, 0x0004
ori r0, r0, 0x0000
C-2
// Set PCI_STAT
// Get old PCI_STAT
// Writing all ones will clear all bits in
// write the modified data to CONFIG_DATA
// Set PICR1 (A8)
// preserve POR bits.
// burst read wt states = 0
// processor type = 603
//enable writes to flash
//enable mcp assertion
//enable data bus parking
//enable address bus parking
// sets the desired bits
// clear snoop wt state bits
// clear addr. phase wt state bits
// clears the undesired bits
// set no-serial-config bit
// Recover RCS1 from PCI
// snoop wt states = 1
// snoop wt states = 0
// addr. phase wt states = 1
// addr. phase wt states = 0
MPC8240 Integrated Processor User's Manual
// Get PICR1 bits
// Get PICR2 bits