Output/Clock Driver And Miscellaneous I/O Control Registers - Motorola MPC8240 User Manual

Output/Clock Driver and Miscellaneous I/O Control Registers

4.4 Output/Clock Driver and Miscellaneous I/O
Control Registers
Table 4-17 describes the general output driver control available with the MPC8240 through
the output driver control register (ODCR), and Table 4-18 describes the output
enable/disable capability available for the clock signals through the clock driver control
register (CDCR).
Output driver control allows for impedance matching of electrical signals. When driving a
capacitive load and the polarity of the driving signal is reversed, the maximum current
driven by the output driver of a pin occurs during the transition of the signal. The output
driver strength must be configured to match the load impedance. The matched impedance
limits the maximum current driven during signal transitions. The transition current and
mismatched impedance cause ringing on the signal. If the driver level is set too strong, the
ringing intensifies. For more information on the output driver type for each signal, refer to
the MPC8240 Hardware Specification.
.
Table 4-17. Output Driver Control Register Bit Definitions—0x73
Bits Name
msb 7 DRV_PCI
addr<73>
6 DRV_STD
5 DRV_MEM_CTRL_1
4-20
Reset
Value
x Driver capability for PCI and EPIC controller output signals. The initial
value of this bit is determined by the PMAA2reset configuration pin.
0 High drive capability on PCI signals (25 Ω)
1 Medium drive capability on PCI signals (50 Ω)
1 Driver capability for standard signals (SDA, SCL, CKO, QACK, MIV,
PMAA[0:2], and MCP).
0 High drive capability on standard signals (20 Ω)
1 Medium drive capability on standard signals (40 Ω)
x Driver capability for the MDH[0:31], MDL[0:31], PAR[0:7], MAA[0:2], and
RCS1 signals. Controlled in combination with DRV_MEM_CTRL_2, as
follows:
1 20-Ω data bus drive capability; when this is selected, only 8-Ω or
13.3-Ω drive capability allowed for DRV_MEM_CTRL_2
0 40-Ω data bus drive capability, when this is selected, only 20-Ω or 40-Ω
drive capability allowed for DRV_MEM_CTRL_2
MPC8240 Integrated Processor User's Manual
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