B-7 Two-Byte Transfer To Pci Memory Space—Little-Endian Mode - Motorola MPC8240 User Manual

Little-Endian Mode
AD[3–0]
Figure B-7. Two-Byte Transfer to PCI Memory Space—Little-Endian Mode
B-10
Processor
A[28–31]
Munge address
XOR with 110
PA[28–31]
0 1 0 0
0 1 2 3 4
xx xx xx xx D4
CDU
Unmunges address
Swaps byte lanes
Runs PCI memory transaction
During address phase
0 0 0 0
(AD[1–0] = 0b00 for memory space access)
3 2 1
D4 D5 xx
D4
PCI Memory Space
MPC8240 Integrated Processor User's Manual
Core
0 0 1 0
Byte lanes
5 6 7
Internal peripheral logic data bus
D5 xx xx
PCI byte lanes (C/BE[3–2] asserted)
0
PCI data bus (AD[31–0] during data phase)
xx
D5 0x00
0x08