Debug Address Signal Definitions - Motorola MPC8240 User Manual

Memory Debug Address
15.3.2 Debug Address Signal Definitions
Table 15-5 describes the mapping of all the memory debug address signals and their
alternate functions. Note that while DA[15:0] are all outputs when used as the debug
address signals, the alternate functions for some of these signals are defined as inputs.
Table 15-5. Memory Debug Address Signal Definitions
Signal
DA[15:11] debug_address[15–11]
DA[10:6] debug_address[10–6]
DA5 debug_address 5
DA4 debug_address 4
DA3 debug_address 3
DA2 debug_address 2
DA1 debug_address 1
DA0 debug_address 0
GNT4 Debug address enable (during reset configuration).
0 Debug address enabled; partial address of the
1 Debug address disabled
15.3.3 Physical Address Mappings
The physical address mappings for 64- and 32-bit DRAM and SDRAM are depicted in
Figure 15-3 and Figure 15-4. The physical address mappings for 64-, 32-, and 8-bit
ROM/Flash are depicted in Figure 15-5, Figure 15-6, and Figure 15-7 respectively. The
encoded version of RAS[0:7] shown in the figures is described in Section 15.3.4, "RAS
Encoding."
Encoded version of RAS[0:7]
0 0
31 30 29 27 26
Figure 15-3. 64-Bit Mode, DRAM and SDRAM Physical Address for Debug
15-6
Signal Meaning
transaction driven on DA[15:0].
DA[15:0]
MPC8240 Integrated Processor User's Manual
Alternate
Function
—
PLL_CFG[0:4]
GNT4
REQ4
PCI_CLK4
—
CKO
QACK
GNT4; DA5
SDMA[7:0] of column address
11 10 9 8 7
Pins I/O
5 O
5 O
1 O
1 O
1 O
1 O
1 O
1 O
1 I
Reserved
0 0 0
3 2 1 0