Motorola MPC8240 User Manual page 250

Integrated host processor with integrated pci
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SDRAM Interface Operation
Therefore, REFINT should be programmed according to the following equation:
Where:
RP is the refresh period of the device = refresh period per bank
memory frequency
x
n = (the number of rows per bank
ROH is the refresh overhead imposed by the MPC8240 and is composed of the
precharge, the PRETOACT interval, the 4 clock cycles to issue the refresh
command, and one dead cycle between refreshes.
TWACC is the worst case access time for the slowest device on the memory bus.
Consider a typical SDRAM device having two internal banks, 2K rows in each bank (4K
rows total) with a refresh period of 32 ms for 2K rows. This means that the MPC8240 must
refresh each internal bank (2K rows) every 32 ms. In this example there are two banks, so
to refresh the whole SDRAM it takes 64 ms. If the memory bus operates at 66 MHz, RP =
64 ms
66 MHz = 4224000 clock cycles to refresh all 4K rows. In this example n = 2048
x
2 ÷ 16 = 256. So, the value of the first term in the REFINT equation above is 4224000 ÷
[(256 + 1)
16] = 1027.237
x
For this example, suppose PRETOACT is set to 2 clock cycles. In this case,
ROH = (2 x 2) + 2 + 4 + 1 = 11
If the system uses 8-bit ROMs on the local memory bus, a burst read from ROM will follow
the timing shown in Figure 6-60. In addition, the minimum time allowed for ROM devices
to enter high impedance is two clock cycles. This delay is enforced after all ROM accesses
preventing any other memory access from starting. Therefore a burst read from an 8-bit
ROM will take:
{[(ROMFAL + 2)
8 + 3]
x
So, if MCCR1[ROMFAL] = 4, the interval for a processor burst read from an 8-bit ROM
will take:
{[(4 + 2)
8 + 3]
4 + 5} + 2 = 211 clock cycles
x
x
Plugging the values into the REFINT equation above:
REFINT < 1027.237 – 11 – (211÷16) = 1003 clock cycles (rounded down)
The value stored in REFINT would be 0b00_0011_1110_1011 (or 1003 clock cycles).
6-32
RP
<
---------------------- -
REFINT
(
n
+
1
)16
the number of banks per device) ÷ 16
x
4 + 5} + 2 clock cycles
x
MPC8240 Integrated Processor User's Manual
16 ROH
(
)
TWACC
----------------------- -
---------------------- -
16
16
the number of banks
x
x

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