Motorola MPC8240 User Manual page 27

Figure
Number
9-11 Inbound Free_FIFO Head Pointer Register (IFHPR) ................................................. 9-15
9-12 Inbound Free_FIFO Tail Pointer Register (IFTPR).................................................... 9-16
9-13 Inbound Post_FIFO Head Pointer Register (IPHPR) ................................................. 9-17
9-14 Inbound Post_FIFO Tail Pointer Register (IPTPR).................................................... 9-17
9-15 Outbound Free_FIFO Head Pointer Register (OFHPR)............................................. 9-18
9-16 Outbound Free_FIFO Tail Pointer Register (OFTPR) ............................................... 9-18
9-17 Outbound Post_FIFO Head Pointer Register (OPHPR) ............................................. 9-19
9-18 Outbound Post_FIFO Tail Pointer Register (OPTPR)................................................ 9-20
9-19 Messaging Unit Control Register (MUCR) ................................................................ 9-20
9-20 Queue Base Address Register (QBAR) ...................................................................... 9-21
2
10-1 I C Interface Block Diagram ...................................................................................... 10-3
2
10-2 I C Interface Transaction Protocol ............................................................................. 10-4
2
10-3 I C Address Register (I2CADR) ................................................................................ 10-7
2
10-4 I C Frequency Divider Register (I2CFDR) ................................................................ 10-8
2
10-5 I C Control Register (I2CCR) .................................................................................. 10-10
2
10-6 I C Status Register (I2CSR) ..................................................................................... 10-11
2
10-7 I C Data Register (I2CDR)....................................................................................... 10-13
2
10-8 Example I C Interrupt Service Routine Flowchart................................................... 10-17
11-1 EPIC Unit Block Diagram .......................................................................................... 11-3
11-2 EPIC Interrupt Generation Block Diagram-Non-programmable Registers ............. 11-9
11-3 Serial Interrupt Interface Protocol ............................................................................ 11-12
11-4 Feature Reporting Register (FRR) ............................................................................ 11-16
11-5 Global Configuration Register (GCR) ...................................................................... 11-16
11-6 EPIC Interrupt Configuration Register (EICR) ........................................................ 11-17
11-7 EPIC Vendor Identification Register (EVI).............................................................. 11-18
11-8 Processor Initialization Register (PI) ........................................................................ 11-19
11-9 Spurious Vector Register (SVR)............................................................................... 11-19
11-10 Timer Frequency Reporting Register (TFRR).......................................................... 11-20
11-11 Global Timer Current Count Register (GTCCR)...................................................... 11-21
11-12 Global Timer Base Count Register (GTBCR) .......................................................... 11-22
11-13 Global Timer Vector/Priority Register (GTVPR)..................................................... 11-22
11-14 Global Timer Destination Register (GTDR)............................................................. 11-24
11-15 Direct and Serial Interrupt Vector/Priority Registers (IVPR and SVPR)................. 11-25
11-16 Direct and Serial Destination Registers (IDR and SDR) .......................................... 11-26
11-17 Processor Current Task Priority Register (PCTPR).................................................. 11-27
11-18 Processor Interrupt Acknowledge Register (IACK) ................................................. 11-28
11-19 Processor End of Interrupt Register (EOI)................................................................ 11-28
12-1 MPC8240 Internal Buffer Organization .................................................................... 12-2
12-2 Processor/Local Memory Buffers ............................................................................... 12-3
12-3 Processor/PCI Buffers................................................................................................. 12-4
12-4 PCI/Local Memory Buffers ........................................................................................ 12-6
12-5 PCI/DMA Arbitration for Local Memory Accesses................................................... 12-9
13-1 Internal Error Management Block Diagram ............................................................... 13-2
ILLUSTRATIONS
Title
Illustrations
Page
Number
xxvii