Motorola MPC8240 User Manual page 597

Bit(s) Name
14 FI Floating-point fraction inexact. The last arithmetic or rounding and conversion instruction either
rounded the intermediate result (producing an inexact fraction) or caused a disabled overflow
exception. This is not a sticky bit. For more information regarding the relationship between
FPSCR[FI] and FPSCR[XX], see the description of the FPSCR[XX] bit.
15–19 FPRF Floating-point result flags. For arithmetic, rounding, and conversion instructions, the field is
based on the result placed into the target register, except that if any portion of the result is
undefined, the value placed here is undefined.
15
16–19
Note that these are not sticky bits.
20 — Reserved
21 VXSOFT Floating-point invalid operation exception for software request. This is a sticky bit. This bit can
be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions.
22 VXSQRT Floating-point invalid operation exception for invalid square root. This is a sticky bit.
23 VXCVI Floating-point invalid operation exception for invalid integer convert. This is a sticky bit.
24 VE Floating-point invalid operation exception enable.
25 OE IEEE floating-point overflow exception enable.
26 UE IEEE floating-point underflow exception enable.
27 ZE IEEE floating-point zero divide exception enable.
28 XE Floating-point inexact exception enable.
29 NI Floating-point non-IEEE mode. If this bit is set, results need not conform with IEEE standards
and the other FPSCR bits may have meanings other than those described here. If the bit is set
and if all implementation-specific requirements are met and if an IEEE-conforming result of a
floating-point operation would be a denormalized number, the result produced is zero (retaining
the sign of the denormalized number). Any other effects associated with setting this bit are
described in the user's manual for the implementation (the effects are
implementation-dependent).
30–31 RN Floating-point rounding control.
00
01
10
11
Table E-4. FPSCR Bit Settings (Continued)
Floating-point result class descriptor (C). Arithmetic, rounding, and conversion
instructions may set this bit with the FPCC bits to indicate the class of the result as
shown in Table E-5.
Floating-point condition code (FPCC). Floating-point compare instructions always
set one of the FPCC bits to one and the other three FPCC bits to zero. Arithmetic,
rounding, and conversion instructions may set the FPCC bits with the C bit to
indicate the class of the result. Note that in this case the high-order three bits of the
FPCC retain their relational significance indicating that the value is less than, greater
than, or equal to zero.
16 Floating-point less than or negative (FL or <)
17 Floating-point greater than or positive (FG or >)
18 Floating-point equal or zero (FE or =)
19 Floating-point unordered or NaN (FU or ?)
Round to nearest
Round toward zero
Round toward +infinity
Round toward –infinity
Appendix E. Processor Core Register Summary
Description
PowerPC Register Set
E-7