Memory Debug Address - Motorola MPC8240 User Manual

PCI_CLK[0:4]
AD[31:0]
C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
PMAA[0:2]
b'111'
Figure 15-2. Example PCI Address Attribute Signal Timing for Burst Write

15.3 Memory Debug Address

When enabled, the debug address gives software disassemblers a simple way to reconstruct
the 30-bit physical address for a memory bus transaction to DRAM, SDRAM, ROM, Flash,
or Port X. For DRAM or SDRAM, these 16 debug address signals are sampled with the
column address and chip-selects. For ROM, Flash, and Port X devices, the debug address
pins are sampled at the same time as the ROM address and can be used to recreate the 24-bit
physical address in conjunction with ROM address. The granularity of the reconstructed
physical address is limited by the bus width of the interface; double words for 64-bit
interfaces, words for 32-bit interfaces, and bytes for 8-bit interfaces.
15.3.1 Enabling Debug Address
The debug address functionality is enabled or disabled at reset by using the GNT4 reset
configuration signal. If the GNT4 signal is left floating at reset, an internal pull-up forces it
high, disabling the debug address functionality. If GNT4 is asserted at reset (driven low),
the debug address functionality is enabled. See Section 2.4, "Configuration Signals
Sampled at Reset," for a complete description of all the reset configuration signals.
Additionally the debug address functionality can be enabled by the setting of the
DEBUG_ADDR_ bit in the WP_CONTROL register. See Section 16.2.4, "Watchpoint
Control Register (WP_CONTROL)," for more information.
ADDR DATA1 DATA2
CMD Byte Enables 1 Byte Enables 2 Byte Enables 3 BEs 4
VALID
Operations
Chapter 15. Debug Features
Memory Debug Address
DATA3 DATA4 T/A
T/A
15-5