Dma Status Registers (Dsrs) - Motorola MPC8240 User Manual

DMA Register Descriptions
The values in the PRC field are used as follows:
• If PRC = 00 (PCI read), then all DMA reads from PCI use the PCI read command.
• If PRC = 01 (PCI read line), then the PCI read line command is used if the PCLSR
(see Section 4.2.5, "PCI Cache Line Size—Offset 0x0C) is programmed for 32-byte
cache lines, and the current DMA transfer is for at least two 32-bit transactions.
Otherwise, PCI read commands are used.
• If PRC = 10 (PCI read multiple), then the PCI read multiple command if used if the
PCLSR is programmed for 32-byte cache lines, the current DMA transfer is aligned
on a cache line address, and more than one full cache line of data is to be transferred.
Otherwise, if the current DMA transfer is for at least two 32-bit transactions (and
less than or equal to one cache line), then the read line command is used. If the
conditions for using the PCI read line command above are not met, then the PCI read
command is used.

8.7.2 DMA Status Registers (DSRs)

The DSRs report various DMA conditions during and after the DMA transfer. Writing a 1
to a set bit clears the bit. Software attempting to determine the source of interrupts should
always perform a logical AND function between the bits of the DSR and their
corresponding enable bits in the DMR and CDAR. Figure 8-5 shows the bits in the DSRs.
31
8-18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-5. DMA Status Register (DSR)
MPC8240 Integrated Processor User's Manual
EOCAI
EOSI
CB
PE
LME
8 7
Reserved
00 0
6 5 4 3 2 1 0