Pci Status Register—0X06 - Motorola MPC8240 User Manual

Reads to this register behave normally. Writes are slightly different in that bits can be
cleared, but not set. A bit is cleared whenever the register is written, and the data in the
corresponding bit location is a 1. For example, to clear bit 14 and not affect any other bits
in the register, write the value 0b0100_0000_0000_0000 to the register.
Received Target-Abort
Received Master-Abort
Signaled System Error
Detected Parity Error
Table 4-6 describes the bit settings for the PCI status register.
Table 4-6. Bit Settings for PCI Status Register—0x06
Bits Name
15 Detected parity error
14 Signaled system error
13 Received
master-abort
12 Received target-abort
11 Signaled target-abort
10–9 DEVSEL timing
8 Data parity detected
7 Fast back-to-back
capable
6 —
5 66-MHz capable
4–0 —
15 14 13 12 11 10 9
Figure 4-4. PCI Status Register—0x06
Reset
Value
0 This bit is set whenever the MPC8240 detects an address or data parity
error, even if parity error handling is disabled (as controlled by bit 6 in
the PCI command register).
0 This bit is set whenever the MPC8240 asserts SERR.
0 This bit is set whenever the MPC8240, acting as the PCI master,
terminates a transaction (except for a special-cycle) using master-abort.
0 This bit is set whenever an MPC8240-initiated transaction is terminated
by a target-abort.
0 This bit is set whenever the MPC8240, acting as the PCI target, issues
a target-abort to a PCI master.
00 These bits are hardwired to 0b00, indicating that the MPC8240 uses
fast device select timing.
0 This bit is set upon detecting a data parity error. Three conditions must
be met for this bit to be set:
• The MPC8240 detected a parity error.
• MPC8240 was acting as the bus master for the operation in which
the error occurred.
• Bit 6 (parity error response) in the PCI command register was set.
1 This bit is hardwired to 1, indicating that the MPC8240 (as a target) is
capable of accepting fast back-to-back transactions.
0 This bit is reserved.
1 This bit is read-only and indicates that the MPC8240 is capable of
66-MHz PCI bus operation.
0_0000 These bits are reserved.
Chapter 4. Configuration Registers
PCI Interface Configuration Registers
Signaled Target-Abort
DEVSEL Timing
Data Parity Detected
Fast Back-to-Back Capable
66-MHz Capable
0 0_0 0 0 0
8 7 6 5 4
Description
Reserved
0
4-13