Interrupt Acknowledge - Motorola MPC8240 User Manual

EPIC Unit Interrupt Protocol

11.3.3 Interrupt Acknowledge

The EPIC unit notifies the processor core of an interrupt by asserting the int signal. When
the processor acknowledges the interrupt request by reading the interrupt acknowledge
register (IACK) in the EPIC unit, the EPIC returns the 8-bit interrupt vector associated with
the interrupt source to the processor through the internal data bus. The interrupt is then
considered to be in service, and it remains in service until the processor performs a write to
the EPIC unit end of interrupt (EOI) register. Writing to the EOI register is referred to as an
EOI cycle.
11.3.4 Nesting of Interrupts
If the processor core is servicing an interrupt, it can only be interrupted again if the EPIC
unit receives an interrupt request from an interrupt source with a priority level greater than
the current task priority (and the in-service interrupt source priority) and if MSR[EE] = 1.
Thus, although several interrupts may be simultaneously in service in the processor, the
code currently executing is always handling the highest priority interrupt of all the
interrupts in service. When the processor performs an EOI cycle, this highest priority
interrupt is taken out of service. The next EOI cycle takes the next highest priority interrupt
out of service, and so forth.
11.3.5 Spurious Vector Generation
Under certain circumstances, the EPIC may not have a valid vector to return to the
processor during an interrupt acknowledge cycle (for example, if there is not a pending
interrupt with a sufficient priority level). In these cases, the spurious vector from the
spurious vector register is returned. The following cases cause a spurious vector fetch:
• int is asserted in response to an externally sourced interrupt which is activated with
level sensitive logic, and the asserted level is negated before the interrupt is
acknowledged.
• int is asserted for an interrupt source that is later masked by the setting of the mask
bit in the vector/priority register before the interrupt is acknowledged.
• int is asserted for an interrupt source that is later masked by an increase in the task
priority level before the interrupt is acknowledged.
• int is not asserted (that is, a programming error causes software to read the IACK
with no interrupt pending).
• int is asserted when there is an illegal clock ratio value in the EPIC interrupt
configuration register.
When there is a spurious interrupt, the interrupt handler should not write to the EOI register.
Otherwise, a previously accepted interrupt might be cleared unintentionally.
11-8 MPC8240 Integrated Processor User's Manual