Fpm Or Edo Dram Address Multiplexing - Motorola MPC8240 User Manual

FPM or EDO DRAM Interface Operation
Table 6-17. Supported FPM or EDO DRAM Device Configurations (Continued)
Devices
DRAM
Devices
64 Mbits

6.3.2 FPM or EDO DRAM Address Multiplexing

System software must configure the MPC8240 at reset to appropriately multiplex the row
and column address bits for each bank. This is done by writing the row address
configuration into the memory control configuration register 1 (MCCR1); see Section 4.10,
"Memory Control Configuration Registers."
The internal physical addresses A[0
pins SDMA[12:0]. The row and column bit configuration settings are shown in Figure 6-32
for 32-bit bus mode and Figure 6-33 for 64-bit bus mode. During the RAS and CAS phases,
the unshaded row and column bits SDMA[12:0] multiplex the appropriate physical
addresses.
6.3.2.1 Row Bit Multiplexing During The Row Phase (RAS)
The following list shows the relationships between the internal physical addresses
A[5 – 20 ] and the external address pins SDMA[12:0] during the assertion of RAS:
msb lsb
• In the 32-bit data bus mode, SDMA12 contains A[6].
• In the 64-bit data bus mode SDMA12 contains A[5].
• If the FPM or EDO has 9 row bits, SDMA[8:0] contains A[12:20].
• If the FPM or EDO has 10 row bits, SDMA[9:0] contains A[11:20].
• If the FPM or EDO has 11 row bits, SDMA[10:0] contains A[10:20].
• If the FPM or EDO has 12 or 13 row bits, SDMA[11:0] contains A[9:20].
Note that SDMA12 is only used as the most-significant row address bit for 13 x 11
FPM or EDO arrays.
6-50
Device
(64-bit
Configuration
Bank)
2 2 Mbits x 32
2 2 Mbits x 32
4 4 Mbits x 16
4 4 Mbits x 16
8 8 Mbits x 8
16 16 Mbits x 4
16 16 Mbits x 4
:31
msb
MPC8240 Integrated Processor User's Manual
64-bit
Row x Column
Bank Size
Bits
(Mbytes)
12 x 9 16
11 x 10 16
12 x 10 32
11 x 11 32
12 x 11 64
13 x 11 128
12 x 12 128
] is multiplexed through the output address
lsb
8 Banks of
Memory
(Mbytes)
128
128
256
256
512
1024
1024