Chip-Select Upper Group Base Address Register; Table 6-5 Chip-Select Group D Base Address Register Description; Table 6-6 Chip-Select Upper Group Base Address Register Description - Motorola MC68VZ328 User Manual

Programming Model
CSGBD Chip-Select Group D Base Address Register
BIT
14 13
15
GB GB GB
D2 D2 D2
8 7
TYPE rw rw rw
0 0
RESET
Table 6-5. Chip-Select Group D Base Address Register Description
Name
GBDx Group D Base Address
–
Bits 15 1 the high-order bits (28–14) of the starting
address for the chip-select range.
Reserved Reserved
Bit 0
6.3.2

Chip-Select Upper Group Base Address Register

The default setting for chip-select decoding limits addressing to A28. When the full address decode enable
(UGEN) bit is set, it allows full address decoding. Full address decoding is enabled for all four of the
chip-select registers by the UGEN bit in the chip-select upper group base address register (CSUGBA). The
bit value of the MSB for each of the four chip-select registers can be written into each of the four MSB
fields in this register. The settings for this register are shown in Table 6-6.
CSUGBA Chip-Select Upper Group Base Address Register
BIT
14 13
15
UG
AGBA[31:29]
EN
TYPE rw rw rw
0 0
RESET
Table 6-6. Chip-Select Upper Group Base Address Register Description
Name
UGEN Full Address Decode Enable—This bit
Bit 15 enables full address range decoding for all
chip-select registers.
AGBA[31:29] MSB for Chip-Select A—The upper most sig-
Bits 14–12 nificant bits for chip-select group A base
address. The value will be ignored if UGEN is
disabled.
6-6
12 11 10
GB GB GB GB
D2 D2 D2 D2
6 5 4 3
rw rw rw rw
0 0 0 0
Description
—
These bits select
12 11 10
BGBA[31:29]
rw rw rw
0 0 0 0
Description
MC68VZ328 User's Manual
9 8 7 6
GB GB GB GB
D2 D2 D1 D1
2 1 0 9
rw rw rw rw
0 0 0 0
0x0000
The chip-select base address must be set
according to the size of the corresponding
chip-select signals of the group.
This bit is reserved and should be set to 0.
9 8 7 6
CGBA[31:29]
rw rw rw
0 0 0 0
0x0000
0 = Ignores A31, A30, and A29.
1 = Decoding includes A31, A30, and A29.
Enter value for bits 31–29 of chip-select regis-
ter A.
0x(FF)FFF106
5 4 3 2
GB GB GB GB
D1 D1 D1 D1
8 7 6 5
rw rw rw rw
0 0 0 0
Setting
0x(FF)FFF108
5 4 3 2
DGBA[31:29]
rw rw rw
0 0 0 0
Setting
BIT
1
0
4
0 0
BIT
1
0
rw
0 0