Fpm Or Edo Dram Power Saving Modes - Motorola MPC8240 User Manual

MCLK
RAS[0,7]
RAS[1,6]
RAS[2,5]
RAS[3,4]
CAS[0:7]
WE
INTERNAL
DATA BUS
Figure 6-44. DRAM Bank Staggered CBR Refresh Timing Configuration

6.3.11 FPM or EDO DRAM Power Saving Modes

The MPC8240's memory interface provides for sleep, doze, and nap power saving modes
defined for the processor core. In doze and nap modes, the MPC8240 supplies normal CBR
refresh to DRAM. In sleep mode, the MPC8240 can be configured to take advantage of
DRAM self-refresh mode, to provide normal refresh to DRAM, or to provide no refresh
support. If the MPC8240 is configured to provide no refresh support in sleep mode, system
software must appropriately preserve DRAM data, that is by copying to disk.
See Chapter 14, "Power Management," for more information on the power saving modes
of the MPC8240.
6.3.11.1 Configuration Parameters for DRAM Power Saving Modes
Table 6-25 provides a summary of the MPC8240 configuration bits relevant to power
saving modes. In Table 6-25, PMCR1 refers to the MPC8240's power management
configuration register 1, and MCCR1 refers to memory control configuration register 1.
RP 1
RC
RPC
CSR
WRP
NOTES:
1. Subscripts identify programmable timing variable (RP1,
RAS 6 P).
2. RAS 6 P = 1–8 cycles.
3. RPs = As configured for read or write timing.
Chapter 6. MPC8240 Memory Interface
FPM or EDO DRAM Interface Operation
RAS 6 P
RAS 6 P
RAS 6 P
RAS 6 P
CHR
WRH
HI-Z
6-67