Motorola MPC8240 User Manual page 73

Table 2-1. MPC8240 Signal Cross Reference (Continued)
Signal
IRQ2 Interrupt 2
IRQ3 Interrupt 3
IRQ4 Interrupt 4
L_INT Local interrupt
LOCK Lock
1
MAA[0:2] Memory addr attributes
1
MCP Machine check
MDH[0:31] Data bus high
MDL[0:31] Data bus low
1
MDL0
MIV Memory interface valid
NMI Nonmaskable interrupt
OSC_IN System clock input
PAR Parity
PAR[0:7] Data parity 0–7
PCI_CLK[0:3] PCI clock outputs
PCI_CLK4/DA3
PCI_SYNC_OUT PCI clock output
PCI_SYNC_IN PCI clock input
PERR Parity error
1
PLL_CFG[0:4] PLL configuration
1
PMAA[0:2] PCI addr. attributes
1
QACK Quiesce acknowledge
RAS[0:7] Row address strobe 0–7
1
RCS0 ROM/bank 0 select
RCS1 ROM/bank 1 select
REQ[3:0] PCI bus request
REQ4/DA4
S_CLK Serial interrupt clock
SCL Serial clock
SDA Serial data
SDBA0 SDRAM bank select 0
SDBA1 SDRAM bank select 1
SDCAS SDRAM column access
strobe
Signal Name Interface
EPIC Control
EPIC Control
EPIC Control
EPIC Control
PCI
Debug
System Control
Memory
Memory
Debug
System Control
Clock
PCI
Memory
Clock
Clock
Clock
PCI
Test/Configurati
on
Debug
Power
Management
Memory
Memory
Memory
PCI
EPIC Control
2
I C Control
2
I C Control
Memory
Memory
Memory
Chapter 2. Signal Descriptions and Clocking
Alternate
Pins
Function (s)
S_RST 1
S_FRAME 1
L_INT 1
IRQ4 1
— 1
— 3
— 1
— 32
— 32
— 1
— 1
— 1
— 1
AR[19:12] 8
PCI_CLK4: 5
DA3
— 1
— 1
— 1
DA[10:6] 5
— 3
DA0 1
CS[0:7] 8
— 1
— 1
REQ0: PCI bus 5
grant
REQ4: DA4
IRQ1 1
— 1
— 1
1
See Table 6-2
1
— 1
Signal Overview
I/O Section #
I/O 2.2.3.1
I/O 2.2.3.1
I/O 2.2.3.1
I/O 2.2.3.3
I 2.2.1.9
O 2.2.5.10.1
O 2.2.5.3
I/O 2.2.2.9
I/O 2.2.2.9
O 2.2.5.10.4
I 2.2.5.4
I 2.2.7.1
I/O 2.2.1.4
I/O 2.2.2.10
O 2.2.7.2
O 2.2.7.3
I 2.2.7.4
I/O 2.2.1.11
I 2.2.6.1
O 2.2.5.10.2
O 2.2.5.8
O 2.2.2.1
O 2.2.2.15
O 2.2.2.16
I 2.2.1.1
I/O
I/O 2.2.3.2.2
I/O 2.2.4.2
I/O 2.2.4.1
O 2.2.2.8
O 2.2.2.8
O 2.2.2.14
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