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8.7 DMA Register Descriptions
The following sections describe the DMA controller registers and their bit settings in detail.
Note that the PCI address offset is listed as part of the register descriptions table titles. For
the local memory offsets, see Table 8-1.
8.7.1 DMA Mode Registers (DMRs)
The DMRs allow software to start the DMA transfer and to control various DMA transfer
characteristics. Figure 8-4 shows the bits in the DMRs.
0 0 0 0 0 0 0 0 0 0
31
CS
CC
CTM
DL
EOTIE
EIE
SAHE
DAHE
SAHTS
DAHTS
PDE
IRQS
LMDC
22 21 20 19 18 17 16 15 14 13 12 11 10 9
Figure 8-4. DMA Mode Register (DMR)
Chapter 8. DMA Controller
DMA Register Descriptions
Reserved
PRC 0
0 0 0
8
7
6
4
3
2
1
0
8-15
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