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Motorola DragonBall MC9328MX1 Manuals
Manuals and User Guides for Motorola DragonBall MC9328MX1. We have
1
Motorola DragonBall MC9328MX1 manual available for free PDF download: Reference Manual
Motorola DragonBall MC9328MX1 Reference Manual (968 pages)
Integrated Portable System Processor
Brand:
Motorola
| Category:
Computer Hardware
| Size: 15.56 MB
Table of Contents
Table of Contents
3
About this Book
51
Document Revision History
54
Block Diagram
57
Features
58
Figure 1-1 MC9328MX1 Functional Block Diagram
58
Chapter 1 Introduction 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
59
AHB to IP Bus Interfaces (Aipis)
59
External Interface Module (EIM)
60
ARM920T Microprocessor Core
59
Clock Generation Module (CGM) and Power Control Module
60
SDRAM Controller (SDRAMC)
60
Two General-Purpose 32-Bit Counters/Timers
61
Watchdog Timer
61
Two Serial Peripheral Interfaces (SPI)
61
LCD Controller (LCDC)
62
Pulse-Width Modulation (PWM) Module
62
Real-Time Clock/Sampling Timer (RTC)
62
Multimedia Card and Secure Digital (MMC/SD) Host Controller
63
Table 1-1 Endpoint Configurations
63
Memory Stick® Host Controller (MSHC)
64
Smartcard Interface Module (SIM)
64
Universal Serial Bus (USB) Device
63
Direct Memory Access Controller (DMAC)
64
Synchronous Serial Interface and Inter-IC Sound (SSI/I 2 S) Module
65
General-Purpose I/O (GPIO) Ports
65
Chapter 9 Bootstrap Mode
65
Video Port
65
Analog Signal Processing (ASP) Module
66
Chapter 16 Bluetooth Accelerator (BTA)
66
Chapter 17 Multimedia Accelerator (MMA)
66
Power Management Features
66
Operating Voltage Range
67
Packaging
67
Table 2-1 MC9328MX1 Signal Descriptions
69
I/O Pads Power Supply and Signal Multiplexing Scheme
76
Table 2-2 MC9328MX1 Signal Multiplexing Scheme
77
Memory Map
87
Memory Space
87
Figure 3-1 MC9328MX1 MCU Physical Memory Map (4 Gbyte)
88
Table 3-1 MCU Memory Space (Physical Addresses)
89
Double Map Image
91
External Memory
91
Internal Register Space
91
On-Chip MCU Memory
91
Internal Registers
92
Table 3-2 MC9328MX1 Internal Registers Sorted by Address
92
Introduction
117
Chapter 3 Memory Map 3.1 Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
118
ARM920T Macrocell
118
Caches
118
Chapter 4 ARM920T Processor 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
118
Figure 4-1 ARM920T Core Functional Block Diagram
118
Cache Lock-Down
119
Mmus
119
Patag Ram
119
System Controller
119
Write Buffer
119
Armv4T Architecture
120
Control Coprocessor (CP15)
120
Modes and Exception Handling
120
Registers
120
Status Registers
120
Conditional Execution
121
Data Processing Instructions
121
Exception Types
121
Four Classes of Instructions
121
Branch Instructions
122
Branch with Link
122
Load and Store Instructions
122
Addressing Modes
122
Block Transfers
122
Coprocessor Instructions
123
Table 4-1 ARM920T Instruction Set
123
The ARM Thumb Instruction Set
124
The ARM9 Instruction Set
123
Table 4-2 ARM Thumb Instruction Set
124
ARM920T Modes and Registers
125
Table 4-3 Register Availability by Mode
125
Introduction to the ETM
127
Figure 5-1 ETM Block Diagram
127
Chapter 5 Embedded Trace Macrocell (ETM) 5.1 Introduction to the ETM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
128
Programming and Reading ETM Registers
128
Pin Configuration for ETM
128
Table 5-1 ETM Pin Configuration
128
Reset Module
129
Chapter 6 Reset Module 6.1 Functional Description of the Reset Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
129
Figure 6-1 Reset Module Block Diagram
129
Functional Description of the Reset Module
129
Global Reset
129
ARM920T Processor Reset
130
Figure 6-2 DRAM and Internal Reset Timing Diagram
130
Clk32
130
Por
130
Clk32
131
Core_Trst
131
Hreset
131
Programming Model
131
Reset_Dram
131
Reset_In
131
Table 6-1 Reset Module Pin and Signal Descriptions
131
Wat_Reset
131
Reset Source Register (RSR)
131
Hard_Asyn_Reset
131
Table 6-2 RSR Register Description
132
Table 6-3 Hardware Reset Source Matrix
132
Features
133
Overview
133
Chapter 7 AHB to IP Bus Interface (AIPI) 7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
133
General Information
133
Figure 7-1 AIPI Interface
134
Figure 7-2 Block Diagram of the AIPI Module
135
Table 7-1 R-AHB to IP Bus Interface Operation (Big Endian-Read Operation)
136
Table 7-2 R-AHB to IP Bus Interface Operation (Big Endian-Write Operation)
138
Table 7-3 R-AHB to IP Bus Interface Operation (Little Endian-Read Operation)
139
Table 7-4 R-AHB to IP Bus Interface Operation (Little Endian-Write Operation)
141
Table 7-5 AIPI Module Register Memory Map
142
Programming Model
142
Table 7-6 Peripheral Address MODULE_EN Numbers
143
Peripheral Size Registers[1:0]
144
Table 7-8 AIPI1 Peripheral Size Register 1 and AIPI2 Peripheral Size Register 1 Description
145
Peripheral Access Registers
146
Table 7-9 PSR Data Bus Size Encoding
146
Peripheral Control Register
147
Table 7-10 Peripheral Access Register Description
147
Time-Out Status Register
148
Table 7-11 Peripheral Control Register Description
148
Data Access to 8-Bit Peripherals
149
Programming Example
149
Table 7-12 Time-Out Status Register Description
149
Data Access to 16-Bit Peripherals
150
Table 7-13 Core and 8-Bit Peripheral Register Content after Code Execution
150
Table 7-14 Core and 16-Bit Peripheral Register Content (Little Endian)
150
Data Access to 32-Bit Peripherals
151
Table 7-15 Core and 16-Bit Peripheral Register Content (Big Endian)
151
Special Consideration for Non-Natural Size Access
152
Table 7-16 Core and 32-Bit Peripheral Register Content (Little Endian)
152
Table 7-17 Core and 32-Bit Peripheral Register Content (Big Endian)
152
Table 8-1 System Control Module Register Memory Map
153
Programming Model
153
Silicon ID Register
154
Table 8-2 Silicon ID Register Description
154
Function Multiplexing Control Register
155
Table 8-3 Function Multiplexing Control Register Description
155
Global Peripheral Control Register
156
Table 8-4 Global Peripheral Control Register Description
157
Global Clock Control Register
158
Table 8-5 Global Clock Control Register Description
158
Table 8-6 System Boot Mode Selection
159
Operation
161
Entering Bootstrap Mode
162
Table 9-1 Bootstrap Record Format
162
Table 9-2 Definition of COUNT/MODE Byte
162
Registers Used in Bootloader Program
163
B-Record Example
163
Changing the Speed of Communication
163
Instruction Buffer Usage
163
Setting up the RS-232 Terminal
163
Table 9-3 Program Breakdown
164
Table 9-4 Resulting B-Records
164
Simple Read/Write Examples
165
Table 9-5 Read/Write Examples
165
Bootloader Flowchart
167
Figure 9-1 Bootloader Program Operation
167
Special Notes
167
Figure 10-1 AITC Block Diagram
169
Introduction
169
Operation
170
AITC Interrupt Controller Signals
171
Table 10-1 Interrupt Assignment
171
Table 10-2 AITC Module Register Memory Map
172
Programming Model
172
Table 10-3 Register Field Summary
174
Interrupt Control Register
175
Table 10-4 Interrupt Control Register Description
175
Normal Interrupt Mask Register
177
Table 10-5 Normal Interrupt Mask Register Description
177
Interrupt Enable Number Register
178
Table 10-6 Interrupt Enable Number Register Description
178
Interrupt Disable Number Register
179
Table 10-7 Interrupt Disable Number Register Description
179
Table 10-8 Interrupt Enable Register High Description
180
Interrupt Enable Register Low
181
Table 10-9 Interrupt Enable Register Low Description
181
Interrupt Type Register High and Interrupt Type Register Low
182
Table 10-10 Interrupt Type Register High Description
182
Interrupt Type Register Low
183
Normal Interrupt Priority Level Registers
183
Table 10-11 Interrupt Type Register Low Description
183
Normal Interrupt Priority Level Register 7
184
Table 10-12 Normal Interrupt Priority Level Register 7 Description
184
Normal Interrupt Priority Level Register 6
185
Table 10-13 Normal Interrupt Priority Level Register 6 Description
185
Normal Interrupt Priority Level Register 5
186
Table 10-14 Normal Interrupt Priority Level Register 5 Description
186
Normal Interrupt Priority Level Register 4
187
Table 10-15 Normal Interrupt Priority Level Register 4 Description
187
Normal Interrupt Priority Level Register 3
188
Table 10-16 Normal Interrupt Priority Level Register 3 Description
188
Normal Interrupt Priority Level Register 2
189
Table 10-17 Normal Interrupt Priority Level Register 2 Description
189
Normal Interrupt Priority Level Register 1
190
Table 10-18 Normal Interrupt Priority Level Register 1 Description
190
Normal Interrupt Priority Level Register 0
191
Table 10-19 Normal Interrupt Priority Level Register 0 Description
191
Normal Interrupt Vector and Status Register
192
Table 10-20 Normal Interrupt Vector and Status Register Description
192
Fast Interrupt Vector and Status Register
193
Table 10-21 Fast Interrupt Vector and Status Register Description
193
Table 10-22 Interrupt Source Register High Description
194
Interrupt Source Register Low
195
Table 10-23 Interrupt Source Register Low Description
195
Interrupt Force Register High and Interrupt Force Register Low
196
Table 10-24 Interrupt Force Register High Description
196
Interrupt Force Register Low
197
Table 10-25 Interrupt Force Register Low Description
197
And Normal Interrupt Pending Register Low
198
Normal Interrupt Pending Register High
198
Table 10-26 Normal Interrupt Pending Register High Description
198
Normal Interrupt Pending Register Low
199
Table 10-27 Normal Interrupt Pending Register Low Description
199
Table 10-28 Fast Interrupt Pending Register High Description
200
Fast Interrupt Pending Register Low
201
Table 10-29 Fast Interrupt Pending Register Low Description
201
AITC Prioritization of Interrupt Sources
202
ARM920T Processor Interrupt Controller Operation
202
ARM920T Processor Prioritization of Exception Sources
202
Assigning and Enabling Interrupt Sources
202
Enabling Interrupts Sources
202
Typical Interrupt Entry Sequences
203
Table 10-30 Typical Hardware Accelerated Normal Interrupt Entry Sequence
203
Table 10-31 Typical Fast Interrupt Entry Sequence
203
Writing Reentrant Normal Interrupt Routines
204
Chapter 11 External Interface Module (EIM) 11.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
205
Address Bus
205
Data Bus
205
Read/Write
206
EIM I/O Signals
205
Overview
205
Chip Select 0 (CS0)
206
Chip Select 1–Chip Select 5 (CS1–CS5)
206
Chip Select Outputs
206
Control Signals
206
Dtack—Data Transfer Acknowledge
206
EB [3:0]—Enable Bytes
206
Oe—Output Enable
206
Burst Mode Signals
207
Bclk—Burst Clock
207
Ecb—End Current Burst
207
Lba—Load Burst Address
207
Pin Configuration for EIM
207
Table 11-1 Chip Select Address Range
207
Table 11-2 EIM Pin List
208
Table 11-3 Pin Configuration
208
Figure 11-1 Example of EIM Interface to Memory and Peripherals
210
Typical EIM System Connections
210
Figure 11-2 Example of EIM Interface to Burst Memory
211
Burst Clock Divisor
212
Burst Mode Operation
212
Configurable Bus Sizing
212
EIM Functionality
212
Programmable Output Generation
212
Burst Clock Start
213
Error Conditions
213
Page Mode Emulation
213
Table 11-4 EIM Module Register Memory Map
214
Programming Model
214
Chip Select 0 Control Registers
215
Chip Select 0 Lower Control Register
215
Chip Select 0 Upper Control Register
215
Chip Select 1–Chip Select 5 Control Registers
216
Table 11-5 Chip Select Control Registers Description
217
Table 11-6 Chip Select Wait State and Burst Delay Encoding
222
EIM Configuration Register
225
Table 11-7 EIM Configuration Register Description
225
Clock Sources
227
Introduction
227
Chapter 12 Phase-Locked Loop and Clock Controller 12.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1 12.2 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
227
Low Frequency Clock Source
227
Figure 12-1 Clock Controller Module
228
High Frequency Clock Source
228
Table 12-1 Clock Controller Module Signal Descriptions
228
DPLL Output Frequency Calculation
229
DPLL Phase and Frequency Jitter
229
ARM920T Processor Low-Power Modes
230
Power Management in the Clock Controller
230
SDRAM Power Modes
230
MC9328MX1 Power Management
230
PLL Operation at Power-Up
230
PLL Operation at Wake-Up
230
Table 12-2 Sdram/Syncflash Operation During Power Modes
230
Clock Source Control Register
231
Programming Model
231
Table 12-3 Power Management in the Clock Controller
231
Table 12-4 PLL and Clock Controller Module Register Memory Map
231
Table 12-5 Clock Source Control Register Description
232
Peripheral Clock Divider Register
234
Table 12-6 Clock Sources for Peripherals
234
Table 12-7 Peripheral Clock Divider Register Description
234
Programming Digital Phase Locked Loops
235
MCU PLL Control Register 0
235
Table 12-8 Sample Frequency Table
235
Table 12-9 MCU PLL Control Register 0 Description
236
MCU PLL and System Clock Control Register 1
237
Generation of 48 Mhz Clocks
237
Table 12-11 System PLL Multiplier Factor
237
System PLL Control Register 0
238
Table 12-12 System PLL Control Register 0 Description
238
System PLL Control Register 1
239
Table 12-13 System PLL Control Register 1 Description
239
Features
241
Figure 13-1 DMAC in MC9328MX1
242
Figure 13-2 DMAC Block Diagram
242
Figure 13-3 DMA Request and Acknowledge Timing Diagram
243
Figure 13-4 2D Memory Diagram
243
Table 13-1 Signal Description
243
Chapter 13 DMA Controller 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 13.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
244
Big Endian and Little Endian
244
Programming Model
244
Table 13-2 DMA Module Register Memory Map
244
General Registers
248
DMA Control Register
248
Table 13-3 DMA Control Register Description
248
DMA Interrupt Status Register
249
Table 13-4 DMA Interrupt Status Register Description
249
DMA Interrupt Mask Register
250
Table 13-5 DMA Interrupt Mask Register Description
250
DMA Burst Time-Out Status Register
251
Table 13-6 DMA Burst Time-Out Status Register Description
251
DMA Request Time-Out Status Register
252
Table 13-7 DMA Request Time-Out Status Register Description
252
DMA Transfer Error Status Register
253
Table 13-8 DMA Transfer Error Status Register Description
253
DMA Buffer Overflow Status Register
254
Table 13-9 DMA Buffer Overflow Status Register Description
254
DMA Burst Time-Out Control Register
255
Table 13-10 DMA Burst Time-Out Control Register Description
255
D Memory Registers (a and B)
256
W-Size Registers
256
Table 13-11 W-Size Registers Description
256
X-Size Registers
257
Table 13-12 X-Size Registers Description
257
Y-Size Registers
258
Channel Registers
258
Table 13-13 Y-Size Registers Description
258
Channel Source Address Register
259
Table 13-14 Channel Source Address Register Description
259
Destination Address Registers
260
Table 13-15 Channel Destination Address Registers Description
260
Channel Count Registers
261
Table 13-16 Channel Count Registers Description
261
Channel Control Registers
262
Table 13-17 Channel Control Registers Description
263
Table 13-18 DMA_EOBO_CNT and DMA_EOBI_CNT Settings
264
Channel Request Source Select Registers
265
Table 13-19 Channel Request Source Select Registers Description
265
Channel Burst Length Registers
266
Table 13-20 Channel Burst Length Registers Description
266
Channel Request Time-Out Registers
267
Channel 0 Bus Utilization Control Register
268
Table 13-21 Channel Request Time-Out Registers Description
268
Table 13-22 Channel 0 Bus Utilization Control Registers Description
269
Table 13-23 DMA Request Table
270
Chapter 14 Watchdog Timer Module
273
Figure 14-1 Watchdog Timer Functional Block Diagram
273
General Overview
273
Watchdog Timer Operation
273
Timing Specifications
273
Countdown
274
Initial Load
274
Power-On Reset
274
Reload
274
Time-Out
275
Software Reset
274
Watchdog after Reset
274
Watchdog During Reset
274
Halting the Counter
275
Interrupt Control
275
Reset Sources
275
Watchdog Control
275
Figure 14-2 Counter State Machine
276
Table 14-1 Watchdog Timer I/O Signals
277
Programming Model
278
Watchdog Control Register
278
Table 14-2 Watchdog Control Register Description
278
Watchdog Service Register
279
Watchdog Status Register
280
Table 14-3 Watchdog Service Register Description
280
Table 14-4 Watchdog Status Register Description
280
Chapter 15 Analog Signal Processor (ASP) 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
283
ASP Signal Description
283
Features
283
Figure 15-1 ASP System Block Diagram
283
Figure 15-2 Simplified ASP Signal Path Diagram
284
Table 15-1 ASP Interface Signal Description
284
Interrupt Generation
285
Pen ADC (PADC) Operation
285
Table 15-2 Simplified ASP Signal Path Parameters
285
Current-Mode Operation
286
Table 15-3 Pen ADC Operation
286
Figure 15-3 Pen Input Sampling Timing
287
Sample Rate Control
287
Table 15-4 Pen ADC Maximum Sample Rate
287
Table 15-5 Output Data Rate Equations
288
Auto-Zero Function
289
Pen-Down Detection
289
Pen-Up Detection (Method 2 – Detect Rising Edge)
289
Temperature Compensation
289
Table 15-6 ASP Module Register Memory Map
290
Programming Model
290
ASP Control Register
291
Table 15-7 Control Register Description
291
Pen A/D Sample Rate Control Register
293
Table 15-8 Pen A/D Sample Rate Control Register Description
293
Compare Control Register
294
Table 15-9 Compare Control Register Description
294
Table 15-10 Interrupt Control Register Description
295
Interrupt/Error Status Register
296
Table 15-11 Interrupt/Error Status Register Description
296
Pen Sample FIFO
297
Clock Divide Register
298
Table 15-12 Pen Sample FIFO Register Description
298
Table 15-13 Clock Divide Register Description
298
ASP FIFO Pointer Register
299
Table 15-14 ASP FIFO Pointer Register Description
299
Bluetooth Primer
301
BTA Overview
302
Figure 16-1 Functional Blocks in a Bluetooth System
302
Figure 16-2 Functional Blocks in the Bluetooth Accelerator
303
IP Bus Interface
304
Module Descriptions
303
Bluetooth Core
303
Table 16-1 CLK_CONTROL Register Settings for Synchronization
304
Sequencer
305
Bluetooth Clocks
305
Table 16-2 Bluetooth Clocks and Counters
305
Interrupt Generation
306
Bluetooth Pipeline Processor
307
Table 16-3 Bluetooth Core Interrupts
307
Figure 16-3 Bluetooth Packet Format
308
HEC/CRC Generator and Checker
308
Table 16-4 Packet Types and FEC/CRC Processing
309
Encryption and Decryption Engine
310
Table 16-5 Writing Sequence for Encryption Engine Initialization
310
FEC Coding/Decoding
311
Bit Buffer
311
Whitening/De-Whitening
311
Correlator
312
Figure 16-4 Bitbuf Memory
312
Table 16-6 Functions Using the Bit Buffer
312
Bluetooth Application Timer
313
Hop Selection Co-Processor
313
Radio Control
313
Table 16-7 Hop Selection Co-Processor Writing Sequence
313
Frequency Synthesizer and Timing Control
314
Pulse Width Modulators
314
Radio Module Interfaces
314
Table 16-8 Bluetooth Pin Mapping for Various Radio Interfaces
314
Figure 16-5 Programming Interfaces for the MC13180 Radio
315
Figure 16-6 Timing of the RF Module Control Signals for the MC13180 Radio
316
Figure 16-7 Programming Interface for the Siwave Radio
317
Figure 16-8 Timing of RF Module Control Signals for the Siwave Radio
317
Figure 16-9 Block Diagram of the Wake-Up Module
318
Figure 16-10 Timing of the Wake-Up Signals
319
Pin Configuration for BTA
319
Table 16-9 Pin Configuration
320
Programming Model
320
Table 16-10 BTA Module Register Memory Map
321
Table 16-11 BTA Module Register Overview
323
Sequencer Registers
326
Command Register
326
Table 16-12 Command Register Description
326
Status Register
327
Table 16-13 Status Register Description
328
Packet Header Register
329
Table 16-14 Packet Header Register Description
329
Payload Header Register
330
Table 16-15 Payload Header Register Description
330
Bluetooth Clocks Registers
331
Native Count Register
331
Table 16-16 Native Count Register Description
331
Estimated Count Register
332
Table 16-17 Estimated Count Register Description
332
Offset Count Register
333
Table 16-18 Offset Count Register Description
333
Native Clock Low Register
334
Table 16-19 Native Clock Low Register Description
334
Native Clock High Register
335
Table 16-20 Native Clock High Register Description
335
Estimated Clock Low Register
336
Table 16-21 Estimated Clock Low Register Description
336
Estimated Clock High Register
337
Table 16-22 Estimated Clock High Register Description
337
Offset Clock Low Register
338
Table 16-23 Offset Clock Low Register Description
338
Offset Clock High Register
339
Table 16-24 Offset Clock High Register Description
339
Bluetooth Pipeline Registers
340
HECCRC Control Register
340
Table 16-25 HECCRC Control Register Description
340
White Control Register
341
Table 16-26 White Control Register Description
341
Encryption Control X13 Register
342
Table 16-27 Encryption Control X13 Register Description
342
Radio Control Registers
343
Correlation Time Setup Register
343
Table 16-28 Correlation Time Setup Register Description
343
Correlation Time Stamp Register
344
Table 16-29 Correlation Time Stamp Register Description
344
RF GPO Register
345
Table 16-30 RF GPO Register Description
345
PWM Received Signal Strength Indicator Register
346
Table 16-31 PWM Received Signal Strength Indicator Register Description (MC13180)
346
Table 16-32 Time a & B Register Description
347
Table 16-33 Time C & D Register Description
348
PWM TX Register
349
Table 16-34 PWM TX Register Description
349
RF Control Register
350
Table 16-35 RF Control Register Description
350
RF Status Register
352
Table 16-36 RF Status Register Description
352
RX Time Register
354
Table 16-37 RX Time Register Description
354
TX Time Register
355
Table 16-38 TX Time Register Description
355
Bluetooth Application Timer Register
356
Timer Register
356
Table 16-39 Bluetooth Application Timer Register Description
356
Correlator Registers
357
Threshold Register
357
Table 16-40 Threshold Register Description (MC13180)
357
Table 16-41 Threshold Register Description (Siliconwave)
358
Table 16-42 Signal Energy Levels and Threshold Levels
358
Correlation Max Register
359
Table 16-43 Correlation Max Register Description
359
Synch Word 0 Register
360
Table 16-44 Synch Word 0 Register Description
360
Synch Word 1 Register
361
Table 16-45 Synch Word 1 Register Description
361
Synch Word 2 Register
362
Synch Word 3 Register
362
Table 16-46 Synch Word 2 Register Description
362
Bit Buffer Registers
363
Buffer Word Registers
363
Table 16-47 Synch Word 3 Register Description
363
Table 16-48 Buf Word 0 (LW0) Register to Buf Word 31 (LW7) Register Description
363
Table 16-49 Bit Buffer Registers Numbers and Addresses
364
Table 16-50 Wake-Up 1 Register Description
365
Wake-Up 2 Register
366
Wake-Up Registers
365
Wake-Up 1 Register
365
Table 16-51 Wake-Up 2 Register Description
366
Wake-Up Delta4 Register
367
Table 16-52 Wake-Up Delta4 Register Description
367
Wake-Up 4 Register
368
Table 16-53 Wake-Up 4 Register Description
368
Wakeup Control Register
369
Table 16-54 Wakeup Control Register Description
369
Wake-Up Status Register
370
Table 16-55 Wake-Up Status Register Description
370
Wake-Up Count Register
371
Table 16-56 Wake-Up Count Register Description
371
System Register
372
Clock Control Register
372
Table 16-57 Clock Control Register Description
372
SPI Registers
373
SPI Word0 Register
373
Table 16-58 SPI Word0 Register Description (MC13180)
373
SPI Word1 Register
374
Table 16-59 SPI Word0 Register Description (Siliconwave)
374
Table 16-60 SPI Word1 Register Description (MC13180)
374
SPI Word2 Register
375
Table 16-61 SPI Word1 Register Description (Siliconwave)
375
Table 16-62 SPI Word2 Register Description (MC13180)
375
Table 16-63 SPI Word2 Register Description (Siliconwave)
375
SPI Word3 Register
376
Table 16-64 SPI Word3 Register Description (MC13180)
376
Table 16-65 SPI Word3 Register Description (Siliconwave)
376
SPI Write Address Register
377
Table 16-66 SPI Write Address Register Description (MC13180)
377
SPI Read Address Register
378
Table 16-67 SPI Write Address Register Description (Siliconwave)
378
Table 16-68 SPI Read Address Register Description (MC13180)
378
SPI Control Register
379
Table 16-69 SPI Read Address Register Description (Siliconwave)
379
Figure 16-11 SPI Clock Dividers Determine Duty Cycle of SPI Clock
380
Table 16-70 SPI Control Register Description
380
SPI Status Register
381
Frequency Hopping Registers
381
Table 16-71 SPI Status Register Description
381
Hop 1 (Frequency In) Register
382
Table 16-72 Hop 0 (Frequency In) Register Description
382
Hop 2 (Frequency In) Register
383
Table 16-73 Hop 1 (Frequency In) Register Description
383
Table 16-74 Hop 2 (Frequency In) Register Description
383
Hop 4 (Frequency In) Register
384
Table 16-75 Hop 3 (Frequency In) Register Description
384
Hop Frequency out Register
385
Table 16-76 Hop 4 (Frequency In) Register Description
385
Table 16-77 Hop Frequency out Register Description
385
Interrupt Register
386
Interrupt Vector Register
386
Table 16-78 Interrupt Vector Register Description
386
Joint Detect Registers
387
Synchronization Metric Register
387
Table 16-79 Synchronization Metric Register Description
387
Synchronize Frequency Carrier Register
388
Bit Reverse Registers
388
Word Reverse Register
388
Table 16-80 Synchronize Frequency Carrier Register Description
388
Byte Reverse Register
389
Table 16-81 Word Reverse Register Description
389
Table 16-82 Byte Reverse Register Description
390
Memory Access
391
MMA Operation
391
Introduction
391
Basic MAC Operation
392
Figure 17-1 MMA Data Access
392
Cache
393
Figure 17-2 Circular Buffering Operation
393
Dct/Idct
394
Figure 17-3 Dct/Idct Architecture
394
Figure 17-4 Data Formatting for DCT and Idct
394
Table 17-1 MMA Module Register Memory Map
395
Programming Model
395
MMA MAC Control Registers
396
MMA MAC Module Register
396
Table 17-2 MMA MAC Module Register Description
396
MMA MAC Control Register
397
Table 17-3 MMA MAC Control Register Description
397
MMA MAC Multiply Counter Register
399
Table 17-4 MMA MAC Multiply Counter Register Description
399
MMA MAC Accumulate Counter Register
400
MMA MAC Interrupt Register
400
Table 17-5 MMA MAC Accumulate Counter Register Description
400
MMA MAC Interrupt Mask Register
401
Table 17-6 MMA MAC Interrupt Register Description
401
Table 17-7 MMA MAC Interrupt Mask Register Description
401
MMA MAC FIFO Register
402
Table 17-8 MMA MAC FIFO Register Description
402
MMA MAC FIFO Status Register
403
Table 17-9 MMA MAC FIFO Status Register Description
403
MMA MAC Bit Select Register
404
MMA MAC Burst Count Register
404
Table 17-10 MMA MAC Burst Count Register Description
404
MMA MAC X Register Control Registers
405
MMA MAC XY Count Accumulate Register
405
Table 17-11 MMA MAC Bit Select Register Description
405
MMA MAC X Base Address Register
406
MMA MAC X Index Register
406
Table 17-12 MMA MAC X Base Address Register Description
406
Table 17-13 MMA MAC X Index Register Description
406
MMA MAC X Length Register
407
Table 17-14 MMA MAC X Length Register Description
407
MMA MAC X Modify Register
408
MMA MAC X Increment Register
408
Table 17-15 MMA MAC X Modify Register Description
408
MMA MAC X Count Register
409
MMA MAC y Register Control Registers
409
Table 17-16 MMA MAC X Increment Register Description
409
Table 17-17 MMA MAC X Count Register Description
409
MMA MAC y Base Address Register
410
MMA MAC y Index Register
410
Table 17-18 MMA MAC y Base Address Register Description
410
Table 17-19 MMA MAC y Index Register Description
410
MMA MAC y Length Register
411
Table 17-20 MMA MAC y Length Register Description
411
MMA MAC y Modify Register
412
MMA MAC y Increment Register
412
Table 17-21 MMA MAC y Modify Register Description
412
MMA MAC y Count Register
413
Table 17-22 MMA MAC y Increment Register Description
413
Table 17-23 MMA MAC y Count Register Description
413
MMA Dct/Idct Registers
414
Dct/Idct Control Register
414
Table 17-24 Dct/Idct Control Register Description
414
Dct/Idct Version Register
415
Table 17-25 Dct/Idct Version Register Description
415
Dct/Idct IRQ Enable Register
416
Table 17-26 Dct/Idct IRQ Enable Register Description
416
Dct/Idct IRQ Status Register
417
Table 17-27 Dct/Idct IRQ Status Register Description
417
Dct/Idct Destination Data Address
418
Dct/Idct Source Data Address
418
Table 17-28 Dct/Idct Source Data Address Register Description
418
Table 17-29 Dct/Idct Destination Data Address Register Description
418
Dct/Idct X-Offset Address
419
Dct/Idct Y-Offset Address
419
Table 17-30 Dct/Idct X-Offset Address Register Description
419
Dct/Idct XY Count
420
Table 17-31 Dct/Idct Y-Offset Address Register Description
420
Table 17-32 Dct/Idct XY Count Register Description
420
Dct/Idct Skip Address
421
Table 17-33 Dct/Idct Skip Address Register Description
421
Dct/Idct Data FIFO
422
Table 17-34 Dct/Idct Data FIFO Register Description
422
Chapter 18 Serial Peripheral Interface Modules (SPI 1 and SPI 2)
423
SPI Block Diagram
423
Table 18-1 SPI 1 and SPI 2 Signal Multiplexing
423
Figure 18-1 SPI Module Block Diagram
424
Phase and Polarity Configurations
424
Operation
424
Figure 18-2 SPI Generic Timing
425
Pin Configuration for SPI 1 and SPI 2
425
Signals
425
Table 18-2 SPI Pin Configuration
426
Table 18-3 SPI Module Register Memory Map
427
Programming Model
427
Receive (RX) Data Registers
428
Table 18-4 SPI 1 Rx Data Register and SPI 2 Rx Data Register Description
428
Table 18-5 SPI 1 Tx Data Register and SPI 2 Tx Data Register Description
429
Control Registers
430
Transmit (TX) Data Registers
429
Table 18-6 SPI 1 Control Register and SPI 2 Control Register Description
430
Table 18-7 SPI 1 Interrupt Control/Status Register and SPI 2 Interrupt Control/Status Register Description
432
Table 18-8 SPI 1 Test Register and SPI 2 Test Register Description
434
Test Registers
434
Table 18-9 SPI 1 Sample Period Control Register and SPI 2 Sample Period Control Register Description
435
DMA Control Registers
436
Soft Reset Registers
437
Table 18-10 SPI 1 DMA Control Register
437
Table 18-11 SPI 1 Soft Reset Register and SPI 2 Soft Reset Register Description
437
Table 19-1 Supported Panel Characteristics
439
Features
439
Introduction
439
Chapter 19 LCD Controller 19.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1
440
Figure 19-1 LCDC Block Diagram
440
Display Data Mapping
441
Panning
441
LCDC Operation
440
LCD Screen Format
440
Figure 19-2 LCD Screen Format
441
Figure 19-3 Pixel Location on Display Screen
442
Figure 19-4 Display Data Mapping, 1/2/4/8 Bpp Modes
443
Table 19-2 Display Mapping in 12 Bpp, CSTN Panel, Little Endian
444
Table 19-3 Display Mapping in 12 Bpp, CSTN Panel, Little Endian
444
Black-And-White Operation
445
Figure 19-5 Display Data Mapping, 16 Bpp Mode
445
Gray-Scale Operation
445
Table 19-4 Display Mapping in 12 Bpp, CSTN Panel, Big Endian
445
Color Generation
446
Figure 19-6 Gray-Scale Pixel Generation
446
Figure 19-7 Passive Matrix Color Pixel Generation
447
Figure 19-8 Active Matrix Color Pixel Generation
447
Frame Rate Modulation Control (FRC)
448
Panel Interface Signals and Timing
448
Table 19-5 Gray Palette Density
448
Figure 19-9 LCDC Interface Signals
449
Pin Configuration for LCDC
449
Table 19-6 Pin Configuration
449
Figure 19-10 LCDC Interface Timing for 4-Bit Data Width Gray-Scale Panels
450
Passive Panel Interface Timing
451
Passive Matrix Panel Interface Signals
450
Figure 19-11 LCDC Interface Timing for 8-Bit Data Passive Matrix Color Panels
451
Active Matrix Panel Interface Signals
452
Figure 19-12 Horizontal Sync Pulse Timing in Passive Mode
452
Figure 19-13 Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode
452
Table 19-7 TFT Color Channel Assignments
453
Active Panel Interface Timing
454
Figure 19-14 LCDC Interface Timing for Active Matrix Color Panels
454
Figure 19-15 Horizontal Sync Pulse Timing in TFT Mode
455
Figure 19-16 Vertical Sync Pulse Timing TFT Mode
455
Table 19-8 LCDC Register Memory Map
456
Programming Model
456
Figure 19-17 Register Memory Mapping Summary
457
Screen Start Address Register
458
Size Register
458
Table 19-9 Screen Start Address Register Description
458
Virtual Page Width Register
459
Table 19-10 Size Register Description
459
Panel Configuration Register
460
Table 19-11 Virtual Page Width Register Description
459
Table 19-12 Panel Configuration Register Description
460
Horizontal Configuration Register
462
Table 19-13 Horizontal Configuration Register Description
462
Vertical Configuration Register
463
Table 19-14 Vertical Configuration Register Description
463
Panning Offset Register
464
Table 19-15 Panning Offset Register Description
464
LCD Cursor Position Register
465
Table 19-16 LCD Cursor X Position Register Description
465
LCD Color Cursor Mapping Register
466
LCD Cursor Width Height and Blink Register
466
Table 19-17 LCD Cursor Width Height and Blink Register Description
466
Table 19-18 LCD Color Cursor Mapping Register Description
467
Sharp Configuration 1 Register
468
Table 19-19 Sharp Configuration 1 Register Description
468
Figure 19-18 Horizontal Timing in MC9328MX1
469
PWM Contrast Control Register
470
Table 19-20 PWM Contrast Control Register Description
470
Table 19-21 Refresh Mode Control Register Description
471
Table 19-22 DMA Control Register Description
472
Interrupt Configuration Register
473
Table 19-23 Interrupt Configuration Register Description
473
Interrupt Status Register
474
Table 19-24 Interrupt Status Register Description
474
Mapping RAM Registers
475
One Bit/Pixel Monochrome Mode
475
Four Bits/Pixel Passive Matrix Color Mode
475
Four Bits/Pixel Active Matrix Color Mode
476
Table 19-26 Four Bits/Pixel Passive Matrix Color Mode
476
Twelve Bits/Pixel and Sixteen Bits/Pixel Active Matrix Color Mode
477
Table 19-28 Four Bits/Pixel Active Matrix Color Mode
477
Features
479
Introduction
479
Figure 20-1 MMC/SD Module Block Diagram
480
Figure 20-2 System Interconnection with MMC/SD Module
480
Chapter 20 Multimedia Card/Secure Digital Host Controller Module (MMC/SD) 20.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 20.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1
481
MMC and SD Card Pin Assignments and Registers
481
MMC/SD Module and Card Information
481
Table 20-1 MMC/SD Card Pin Assignment
481
Table 20-2 MMC/SD Card Registers
481
Communication
482
Pin Configuration for the MMC/SD Module
483
Functional Description
483
Signal Description
483
Table 20-3 Pin Configuration
483
DMA Interface
484
Figure 20-3 DMAC Interface Block Diagram
484
DMA Burst Request
485
Write-Error Detection
486
Figure 20-4 FIFO Usage for Different Modes
486
Card Detection
487
SD I/O—IRQ and Readwait Service Handling
487
Memory Controller (Register Handler)
486
Figure 20-5 Memory Controller Block Diagram
487
Figure 20-6 Card Detection Mechanism
488
Logic and Command Interpreters
488
MMC/SD Module Interrupt Handling
488
Figure 20-7 Block Diagram for Logic and Command Interpreters
489
Figure 20-8 Command CRC Shift Register (SD_DAT Has a Similar Structure)
490
Figure 20-9 Clock Tree for the MMC/SD Module
490
System Clock Controller
490
Card Clock Control
491
Programming Model
491
Figure 20-10 System Clock Control Unit
491
Table 20-4 Multimedia Controller Register Memory Map
491
MMC/SD Clock Control Register
492
Table 20-5 MMC/SD Clock Control Register Description
493
MMC/SD Status Register
494
Table 20-6 MMC/SD Status Register Description
494
MMC/SD Clock Rate Register
497
Table 20-7 MMC/SD Clock Rate Register Description
497
MMC/SD Command and Data Control Register
498
Table 20-8 MMC/SD Command and Data Control Register Description
498
MMC/SD Response Time-Out Register
499
MMC/SD Read Time-Out Register
500
Table 20-10 MMC/SD Read Time-Out Register Description
500
MMC/SD Block Length Register
501
Table 20-9 MMC/SD Response Time-Out Register Description
500
Table 20-11 MMC/SD Block Length Register Description
501
MMC/SD Number of Blocks Register
502
Table 20-12 MMC/SD Number of Blocks Register Description
502
MMC/SD Revision Number Register
503
Table 20-13 MMC/SD Revision Number Register Description
503
MMC/SD Interrupt Mask Register
504
Table 20-14 MMC/SD Interrupt Mask Register Description
504
Table 20-15 Interrupt Mechanisms
505
Commands and Arguments
506
MMC/SD Command Number Register
507
MMC/SD Higher Argument Register
507
Table 20-16 MMC/SD Command Number Register Description
507
MMC/SD Lower Argument Register
508
Table 20-17 MMC/SD Higher Argument Register Description
508
Table 20-18 MMC/SD Lower Argument Register Description
508
MMC/SD Response FIFO Register
509
Table 20-19 MMC/SD Response FIFO Register Description
509
MMC/SD Buffer Access Register
510
Functional Example for the MMC/SD Module
510
Table 20-20 MMC/SD Buffer Access Register Description
510
Basic Operation
511
Card Detect
511
Card Identification State
511
Reset
512
Voltage Validation
512
Card Registry
513
Card Access
515
Block Access—Block Write and Block Read
515
Block Write
515
Block Read
517
Stream Access—Stream Write and Stream Read (MMC Only)
520
Stream Write
520
Stream Read
521
Erase—Group Erase and Sector Erase (MMC Only)
522
Wide Bus Selection or Deselection
523
Card Internal Write Protection
523
Protection Management
523
Mechanical Write Protect Switch
524
Password Protect
524
Table 20-21 Structure of Command Data Block
524
Locking a Card
525
Resetting the Password
525
Setting the Password
525
Forcing Erase
526
Card Status Register
527
Unlocking the Card
526
Table 20-22 Card Status Register Description
527
SD Status Register
529
Sd I/O
530
SD I/O Interrupts
530
Table 20-23 SD Status Register
530
SD I/O Readwait
531
Commands and Responses
532
SD I/O Suspend and Resume
531
Application-Specific and General Commands
533
Command Formats
533
Command Types
533
Commands for the MMC/SD Module
534
Table 20-24 Command Format
534
Table 20-25 Commands for MMC/SD Module
534
R1—Normal Response
538
Response Formats
538
R1B—Normal Response with Busy
539
R2—CID, CSD Register
539
R3—OCR Register
539
R4—Fast I/O for MMC Only
539
Table 20-26 R1 Response
539
Table 20-27 R2 Response
539
Table 20-28 R3 Response
539
R4B—Sd I/O Only
540
R5—Interrupt Request (for MMC Only)
540
R6—SD I/O Only
540
Table 20-29 R4 Response
540
Table 20-30 R4B Response
540
Table 20-31 R5 Response
540
Table 20-32 R6 Response
541
Chapter 21 Memory Stick Host Controller (MSHC) Module 21.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1 21.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21-1
543
Block Diagram and Description
543
Chapter 29 I C Module
543
Overview
543
Features
543
Figure 21-1 Memory Stick Host Controller Simplified Block Diagram
544
Memory Stick Interface
544
Figure 21-2 Memory Stick Interface
545
Pin Configuration for the MSHC Module
545
Signal Description
545
Data FIFO Operation
546
Memory Stick Host Controller Operation
546
Table 21-1 Pin Configuration
546
Bus State Control Operation
547
Interrupt Sources
547
MSHC Module Interrupt Operation
547
Table 21-2 MSHC Module Interrupt Sources Summary
547
SDIO Interrupt Operation
548
Figure 21-3 Memory Stick Interrupt Transfer State (BS0) Operation
548
Reset Operation
549
Power Save Mode Operation
550
Figure 21-4 Power Save Mode
550
Table 21-3 Interrupt Detect Capability on Power Save Mode
550
Register Access During Power Save Mode
551
Register Access When MSHC Module Is Disabled
551
Auto Command Function
551
Figure 21-5 Auto Command Function Operation
552
Serial Clock Divider Operation
553
Figure 21-6 MSHC Module Serial Clock Divider
553
System-Level DMA Transfer Operation
553
Table 21-4 Serial Clock Divider Settings
553
Programming Model
554
Table 21-5 MSHC Module DMA Configuration Options
554
Table 21-6 MSHC Module Register Memory Map
554
Memory Stick Command Register
555
Table 21-7 Memory Stick Command Register Description
555
Memory Stick Control/Status Register
556
Table 21-8 Memory Stick Control/Status Register Description
556
Memory Stick Transmit FIFO Data Register
557
Memory Stick Receive FIFO Data Register
558
Table 21-9 Memory Stick Transmit FIFO Data Register Description
558
Memory Stick Interrupt Control/Status Register
559
Table 21-10 Memory Stick Receive FIFO Data Register Description
559
Table 21-11 Memory Stick Interrupt Control/Status Register Description
559
Memory Stick Parallel Port Control/Data Register
561
Table 21-12 Memory Stick Parallel Port Control/Data Register Description
561
Memory Stick Control 2 Register
562
Table 21-13 Memory Stick Control 2 Register Description
562
Memory Stick Auto Command Register
563
Memory Stick FIFO Access Error Control/Status Register
563
Table 21-14 Memory Stick Auto Command Register Description
563
Memory Stick Serial Clock Divider Register
564
Table 21-15 Memory Stick FIFO Access Error Control/Status Register Description
564
Memory Stick DMA Request Control Register
565
Table 21-16 Memory Stick Serial Clock Divider Register Description
565
Memory Stick Serial Interface Overview
566
Programmer's Reference
566
Table 21-17 Memory Stick DMA Request Control Register Description
566
Figure 21-7 Memory Stick Bus Four State Access Protocol
567
Table 21-18 Serial Interface Signal Specifications
567
Table 21-19 Four State Access Mode
567
Figure 21-8 Write Packet
568
Figure 21-9 Read Packet
568
Protocol
568
Table 21-20 Write Packet
568
Table 21-21 Read Packet
569
Table 21-22 TPC Code Specification
569
Transfer Protocol Command (TPC)
569
Figure 21-10 Two State Access Mode
570
Protocol Error
570
Overview
570
Figure 21-11 Write Packet Time-Out
571
Figure 21-12 Read Packet Time-Out
571
Table 21-23 Bus State in Two State Access Mode
571
Figure 21-13 Signal Timing
572
Table 21-24 Two State Access Mode Factor
572
Data Transfer Extension
573
Figure 21-14 Bus State Extension
573
Figure 21-15 SCLK Extension for Data Wait
573
Chapter 22 Pulse-Width Modulator (PWM) 22.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1
575
Clock Signals
575
Figure 22-1 Pulse-Width Modulator Block Diagram
575
PWM Signals
575
Introduction
575
Figure 22-2 Audio Waveform Generation
576
Pin Configuration for PWM
576
Playback Mode
576
PWM Operation
576
Table 22-1 Pin Configuration
576
Table 22-2 PWM Module Register Memory Map
577
Tone Mode
577
Programming Model
577
PWM Control Register
577
Table 22-3 PWM Control Register Description
578
HCTR and BCTR Bit Description
579
PWM Sample Register
580
Table 22-4 HCTR and BCTR Bit Swapping
580
Table 22-5 PWM Sample Register Description
580
PWM Period Register
581
Table 22-6 PWM Period Register Description
581
PWM Counter Register
582
Table 22-7 PWM Counter Register Description
582
Chapter 23 Real-Time Clock (RTC) 23.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23-2
584
Figure 23-1 Real-Time Clock Block Diagram
584
Operation
584
Prescaler and Counter
584
Chapter 26 General-Purpose Timers
584
Alarm
585
Sampling Timer
585
Minute Stopwatch
585
Table 23-1 Sampling Timer Frequencies
585
Programming Model
586
RTC Days Counter Register
586
Table 23-2 RTC Module Register Memory Map
586
RTC Hours and Minutes Counter Register
587
Table 23-3 RTC Days Counter Register Description
587
Table 23-4 RTC Hours and Minutes Counter Register Description
587
RTC Seconds Counter Register
588
Table 23-5 RTC Seconds Counter Register Description
588
RTC Day Alarm Register
589
Table 23-6 RTC Day Alarm Register Description
589
RTC Hours and Minutes Alarm Register
590
Table 23-7 RTC Hours and Minutes Alarm Register Description
590
RTC Seconds Alarm Register
591
Table 23-8 RTC Seconds Alarm Register Description
591
RTC Control Register
592
RTC Interrupt Status Register
592
Table 23-9 RTC Control Register Description
592
Table 23-10 RTC Interrupt Status Register Description
593
RTC Interrupt Enable Register
595
Table 23-11 RTC Interrupt Enable Register Description
595
Stopwatch Minutes Register
597
Table 23-12 Stopwatch Minutes Register Description
597
Features
599
Figure 24-1 SDRAM Controller Block Diagram
600
Chapter 24 SDRAM Memory Controller 24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24-1 24.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
601
Configuration Registers
601
Refresh Request Counter
601
Powerdown Timer
602
Data Aligner and Multiplexer
601
Functional Overview
601
Page and Bank Address Comparators
601
Row and Column Address Multiplexer
601
SDRAM Command Controller
601
DMA Operation with the SDRAM Controller
602
External Interface
602
Table 24-1 AHB Bus and Internal Interface Signals
602
Table 24-2 SDRAM Interface Pin Characteristics
602
CSD0, CSD1—SDRAM Chip-Select
603
SDCKE0, SDCKE1—SDRAM Clock Enables
603
SDCLK—SDRAM Clock
603
DQ [31:0]—Data Bus (Internal)
604
DQM3, DQM2, DQM1, Dqm0—Data Qualifier Mask
604
MA [11:0]—Multiplexed Address Bus
604
Ras—Row Address Strobe
604
SDBA [4:0], SDIBA [3:0]—Non-Multiplexed Address Bus
604
Sdwe—Write Enable
604
Cas—Column Address Strobe
605
Reset_Sf—Reset or Powerdown
605
Pin Configuration for SDRAMC
605
Table 24-4 Pin Configuration
605
Programming Model
606
Table 24-5 SDRAM Module Register Memory Map
606
Chapter 8 System Control
606
Table 24-6 SDRAM Array Memory Map
606
SDRAM Control Registers
607
Table 24-7 SDRAM 0 Control Register and SDRAM 1 Control Register Description
607
Figure 24-2 Memory Bank Interleaving Options
611
Table 24-8 Settings for SREFR Field
611
Figure 24-3 cas Latency Timing
612
Figure 24-4 Precharge Delay Timing
613
Figure 24-5 Row-To-Column Delay Timing
613
SDRAM Reset Register
614
Figure 24-6 Row Cycle Timing
614
Table 24-9 SDRAM Reset Register Description
614
Miscellaneous Register
615
Table 24-10 Miscellaneous Register Description
615
Operating Modes
616
Table 24-11 SDRAM and Syncflash Command Encoding
616
Normal Read/Write Mode (SMODE = 000)
617
Figure 24-7 Off-Page Single Read Timing Diagram (32-Bit Memory)
618
Figure 24-8 On-Page Single Read Timing Diagram (32-Bit Memory)
618
Figure 24-10 On-Page Burst Read Timing Diagram (32-Bit Memory)
619
Figure 24-11 Off-Page Write Followed by On-Page Write Timing Diagram
619
Figure 24-9 Off-Page Burst Read Timing Diagram (32-Bit Memory)
619
Figure 24-12 Off-Page Burst Write Timing Diagram
620
Figure 24-13 On-Page Burst Write Timing Diagram
620
Figure 24-14 Single Write Followed by On-Page Read Timing Diagram
620
Figure 24-15 Burst Write Followed by On-Page Read Timing Diagram
621
Figure 24-16 Single Read Followed by On-Page Write Timing Diagram
621
Figure 24-17 Burst Read Followed by On-Page Write Timing Diagram
621
Precharge Command Mode (SMODE = 001)
621
Auto-Refresh Mode (SMODE = 010)
622
Figure 24-18 Precharge Bank Timing Diagram
622
Figure 24-19 Precharge All Timing Diagram
622
Figure 24-20 Software Initiated Auto-Refresh Timing Diagram
623
Set Mode Register Mode (SMODE = 011)
623
Figure 24-21 Set Mode Register State Diagram
624
Figure 24-22 Set Mode Register Timing Diagram
624
Syncflash Program Mode
625
Syncflash Load Command Mode
624
Figure 24-23 Load Command Register Timing Diagram
625
Figure 24-24 Syncflash Program Mode State Diagram
625
Figure 24-25 Syncflash Program Timing Diagram
626
Figure 24-26 Syncflash Read Status Register Timing Diagram
626
Address Multiplexing
627
General Operation
626
Multiplexed Address Bus
627
Table 24-12 JEDEC Standard Single Data Rate Sdrams
627
Table 24-13 Address Multiplexing by Column Width
628
Table 24-14 MC9328MX1 to SDRAM Interface Connections
628
Non-Multiplexed Address Bus
629
Bank Addresses
630
Refresh
630
Figure 24-27 Hardware Refresh Timing Diagram
630
Figure 24-28 Hardware Refresh with Pending Bus Cycle Timing Diagram
631
Powerdown Operation During Reset and Low-Power Modes
631
Self-Refresh
631
Self-Refresh During Low-Power Mode
631
Self-Refresh During RESET_IN
631
Figure 24-29 Self-Refresh Entry Due to Low-Power Mode Timing Diagram
632
Figure 24-30 Low-Power Mode Self-Refresh Exit Timing Diagram
632
Clock Suspend Low-Power Mode
633
Figure 24-31 Powerdown Mode Resulting from Reset with Refresh Disabled
633
Powerdown
633
Clock Suspend
634
Figure 24-32 Powerdown Mode Entry Timing Diagram
634
Figure 24-33 Powerdown Exit Timing Diagram
634
Refresh During Powerdown or Clock Suspend
634
Configuring Controller for SDRAM Memory Array
635
Figure 24-34 Clock Suspend Timing Diagram
635
CAS Latency
636
SDRAM Operation
635
SDRAM Selection
635
Refresh Rate
636
Row Cycle Delay
636
Row Precharge Delay
636
Row-To-Column Delay
636
Figure 24-35 Single 64 Mbit (4M X 16) Connection Diagram (IAM = 1)
637
Memory Configuration Examples
637
Table 24-15 Single 4M X 16 Control Register Values
637
Figure 24-36 Single 64 Mbit (4M X 16 X 1) Connection Diagram (IAM = 0)
638
Table 24-16 Single 4M X 16 Control Register Values
638
Figure 24-37 Single 128 Mbit (8M X 16) Connection Diagram (IAM = 1)
639
Table 24-17 Single 8M X 16 Control Register Values
639
Figure 24-38 Single 128 Mbit (8M X 16) Connection Diagram (IAM = 0)
640
Table 24-18 Single 8M X 16 Control Register Values
640
Figure 24-39 Single 256 Mbit (16M X 16) Connection Diagram (IAM = 1)
641
Table 24-19 Single 16M X16 Control Register Values
641
Figure 24-40 Single 256 Mbit (16M X 16) Connection Diagram (IAM = 1)
642
Table 24-20 Single 16M X16 Control Register Values
642
Figure 24-41 Dual 64 Mbit (4M X 16 X 2) Connection Diagram (IAM = 1)
643
Table 24-21 Dual 64 Mbit (4M X 16 X 2) Control Register Values (IAM = 1)
643
Figure 24-42 Dual 64 Mbit (4M X 16 X 2) Connection Diagram (IAM = 0)
644
Table 24-22 Dual 64 Mbit (4M X 16 X 2) Control Register Values (IAM = 0)
644
Figure 24-43 Dual 128 Mbit (8M X 16 X 2) Connection Diagram (IAM = 1)
645
Table 24-23 Dual 128 Mbit (8M X 16 X 2) Control Register Values (IAM = 1)
645
Figure 24-44 Dual 128 Mbit (8M X 16 X 2) Connection Diagram (IAM = 0)
646
Table 24-24 Dual 128 Mbit (8M X 16 X 2) Control Register Values (IAM = 0)
646
Figure 24-45 Dual 256 Mbit (16M X 16 X 2) Connection Diagram (IAM = 1)
647
Table 24-25 Dual 256 Mbit (16M X 16 X 2) Control Register Values (IAM = 1)
647
Figure 24-46 Dual 256 Mbit (16M X 16 X 2) Connection Diagram (IAM = 0)
648
Table 24-26 Dual 256 Mbit (16M X 16 X 2) Control Register Values (IAM = 0)
648
Figure 24-47 Single 64 Mbit (2M X 32) Connection Diagram (IAM = 1)
649
Table 24-27 Single 64 Mbit (2M X 32) Control Register Values (IAM = 1)
649
Figure 24-48 Single 64 Mbit (2M X 32) Connection Diagram (IAM = 0)
650
Table 24-28 Single 64 Mbit (2M X 32) Control Register Values
650
Figure 24-49 Single 128 Mbit (4M X 32) Connection Diagram (IAM = 1)
651
Table 24-29 Single 128 Mbit (4M X 32) Control Register Values (IAM = 1)
651
Figure 24-50 Single 128 Mbit (4M X 32) Connection Diagram (IAM = 0)
652
Table 24-30 Single 128 Mbit (4M X 32) Control Register Values (IAM = 0)
652
Figure 24-51 Single 256 Mbit (8M X 32) Connection Diagram (IAM = 1)
653
Table 24-31 Single 256 Mbit (8M X 32) Control Register Values (IAM = 1)
653
Figure 24-52 Single 256 Mbit (8M X 32) Connection Diagram (IAM = 0)
654
SDRAM Reset Initialization
654
Table 24-32 Single 256 Mbit (8M X 32) Control Register Values (IAM = 0)
654
Figure 24-53 SDRAM Power-On Initialization Sequence
655
Mode Register Programming
656
Table 24-33 4M X 16 Memory Configuration
656
Table 24-34 8M X 16 Memory Configuration
657
Table 24-35 16M X 16 Memory Configuration
657
Table 24-36 2M X 32 Memory Configuration
657
Table 24-37 4M X 32 Memory Configuration
657
Table 24-38 8M X 32 Memory Configuration
657
Table 24-39 MC9328MX1 SDRAM Memory Configuration
658
Mode Register Programming Examples
659
Example 1—256 Mbit SDRAM Mode Register
659
Table 24-40 256 Mbit SDRAM Mode Register
659
Table 24-41 256 Mbit SDRAM Mode Register Description
659
Table 24-42 256 Mbit SDRAM Mode Register with Values
660
Table 24-43 MC9328MX1 Address Calculation for Given Mode Register Values
660
Example 2—64 Mbit SDRAM Mode Register
661
Table 24-44 64 Mbit SDRAM Mode Register
661
Table 24-45 64 Mbit SDRAM Mode Register Description
661
Table 24-46 64 Mbit SDRAM Mode Register with Values
662
Table 24-47 MC9328MX1 Address Calculation for Given Mode Register Value
662
Syncflash Operation
663
Syncflash Reset Initialization
663
Table 24-48 SDRAM Memory Refresh
663
Booting from Syncflash
664
Figure 24-54 Sync Flash Reset Timing
664
Syncflash Configuration
664
Syncflash Mode Register Programming
664
Figure 24-55 Single 64 Mbit Syncflash Connection Diagram (IAM = 0)
665
Table 24-49 Single 4M X 16 Syncflash Control Register Values
665
Table 24-50 Dual 4M X 16 Syncflash Control Register Values (IAM = 0)
665
Figure 24-56 Dual 64 Mbit Syncflash Connection Diagram (IAM = 0)
666
Clock Suspend Timer Use with Syncflash
667
Syncflash Programming
666
Table 24-51 Syncflash Command Sequences
667
Deep Powerdown Operation with Syncflash
668
Figure 24-57 Syncflash Clock Suspend Timer Operation Timing Diagram
668
Figure 24-59 Syncflash Deep Powerdown Operation Timing Diagram
669
Figure 25-1 SIM Simplified Block Diagram
671
IP Bus Interface
671
Module Overview
671
SIM Clock Generator
672
SIM Transmitter
672
SIM Receiver
672
Table 25-1 SIM Transmitter Interrupt Summary
672
SIM General Purpose Counter
673
SIM Port Control
673
SIM LRC and CRC
673
Table 25-2 SIM Receiver Interrupt Summary
673
Table 25-3 SIM Port Control Interrupt Summary
673
Table 25-4 SIM Port Control Interrupt Summary
673
Functional Description
674
SIM Clock Generator
674
Baud Clock Generation
674
Figure 25-2 SIM Clock Generator Diagram
674
Port Controller Clock Generation
675
SIM Transmitter
675
Transmit State Machine
675
Receiver Clock Generation
675
Transmitter Clock Generation
675
Figure 25-3 Transmit State Machine Operation Diagram
676
Transmit Guard Time Generator
677
Transmit Shift Register
677
Transmit FIFO
677
Figure 25-4 Transmit Guard Time Diagram
678
Figure 25-5 Transmit NACK Operation
678
Transmit NACK Generator
678
Figure 25-6 SIM Data Conventions
679
Transmit Data Convention Logic
679
Receive State Machine
679
SIM Receiver
679
Data Sampling / Voting
681
Figure 25-7 Receive State Machine Diagram
681
Figure 25-8 Start Bit Diagram
681
Parity Error Detection
681
Start Bit Detection
681
Figure 25-10 Framing Error Diagram
682
Figure 25-9 Parity Bit Diagram
682
Framing Error Detection
682
NACK Detection
682
Initial Character Detection
683
Figure 25-11 Valid Initial Characters
683
Figure 25-12 Inverse Convention Vs. Direct Convention
683
Receive FIFO
683
Character Wait Time Counter
684
Overrun Detection
684
SIM Port Controller
684
Chapter 25 Smartcard Interface
684
Figure 25-13 Two Methods of Smartcard Hookup to MC9328MX1 SIM Port
685
Smartcard Automatic Powerdown
685
Smartcard Presence Detect
685
Figure 25-14 Automatic Powerdown Sequence
686
SIM General Purpose Counter
686
SIM LRC Block
686
Figure 25-15 Cyclic Redundancy Check Circuit Diagram
687
SIM CRC Block
687
Pin Configuration for SIM
688
Table 25-5 SIM Interrupts
688
Table 25-6 Pin Configuration
689
Programming Model
689
Table 25-7 SSI Module Register Memory Map
689
Table 25-8 Register Field Summary
690
Port Control Register
692
Table 25-9 Port Control Register Descriptions
692
Control Register
693
Table 25-10 Control Register Descriptions
693
Receive Threshold Register
695
Table 25-11 Receive Threshold Register Description
696
Table 25-12 Transmit/Receive Enable Register Description
696
Transmit/Receive Enable Register
696
Table 25-13 Transmit Status Register Description
697
Transmit Status Register
697
Receive Status Register
699
Table 25-14 Receive Status Register Description
699
Interrupt Mask Register
701
Table 25-15 Interrupt Mask Register Description
701
Port Transmit Buffer Register
702
Table 25-16 Port Transmit Buffer Register Description
702
Receive Buffer Register
703
Table 25-17 Receive Buffer Register Description
703
Port Detect Register
704
Table 25-18 Port Detect Register Description
704
Table 25-19 Transmit Threshold Register Description
705
Transmit Threshold Register
705
Table 25-20 Transmit Guard Control Register Description
706
Transmit Guard Control Register
706
Open-Drain Configuration Control Register
707
Table 25-21 Open-Drain Configuration Control Register Description
707
Table 25-22 Reset Control Register Description
708
Character Wait Timer Register
709
Table 25-23 Character Wait Timer Register Description
709
General Purpose Counter Register
710
Table 25-24 General Purpose Counter Register Description
710
Divisor Register
711
Functional Programming Example
711
Table 25-25 Divisor Register Description
711
Table 25-26 Configuring the SIM for Operation
711
Table 25-27 Configuring the SIM Receiver
712
Table 25-28 Configuring the SIM Transmitter
713
Table 25-29 Configuring the SIM General Purpose Counter
714
Table 25-30 Configuring the SIM Linear Redundancy Check Block
714
Table 25-31 Configuring the SIM Cyclic Redundancy Check Block
715
Using the SIM Receiver
715
Receive Frame Errors
716
Receive Overrun Errors and Overrun NACK Generation
716
Receive Parity Errors and Parity NACK Generation
716
Initial Character Mode Programming
717
Using Initial Character Mode and Resulting Receive Data Formats
717
Automatic Receiver Mode
718
Using the SIM Receiver with T = 1 Smartcards
718
Using the SIM Transmitter
718
Transmit Data Formats
719
Transmit Nacks
719
Transmit Guard Time
720
Using the SIM Transmit with T = 1 Smartcards
720
Answer to Reset (ATR) Detection
721
Suggested Programming Models for Specific Smartcards
721
Programming Considerations
722
Figure 25-16 Suggested T = 1, EMV, and Geldkate Compliant SIM Initialization
723
Geldkate Cards
723
T = 0 Smartcards
723
T = 1 Smartcards
724
Figure 26-1 General-Purpose Timers Block Diagram
727
Operation
728
Pin Configuration for General-Purpose Timers
728
Chapter 10 Interrupt Controller (AITC) 10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
728
Table 26-1 Pin Configuration
728
Table 26-2 GP Timers Module Register Memory Map
729
Timer Control Registers 1 and 2
729
Programming Model
729
Table 26-3 Timer 1 and 2 Control Registers Description
730
Timer Prescaler Registers 1 and 2
731
Table 26-4 Timer 1 and 2 Prescaler Registers Description
731
Timer Compare Registers 1 and 2
732
Table 26-5 Timer 1 and 2 Compare Registers Description
732
Timer Capture Registers 1 and 2
733
Table 26-6 Timer 1 and 2 Capture Registers Description
733
Timer Counter Registers 1 and 2
734
Table 26-7 Timer 1 and 2 Counter Registers Description
734
Timer Status Registers 1 and 2
735
Table 26-8 Timer 1 and 2 Status Registers Description
735
Features
737
Introduction
737
Module Interface
738
Table 27-1 UART Module Interface Signals
738
Chapter 27 Universal Asynchronous Receiver/Transmitters (UART) Modules 27.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1 27.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27-1
739
Pin Configuration for UART1 and UART2
739
Table 27-2 Pin Configuration
739
Table 27-3 Interrupts and DMA
740
General UART Definitions
741
RTS Edge Triggered Interrupt
742
RTS—UART Request to Send
742
Figure 27-1 General Connections for a UART with a Modem
742
Table 27-4 RTS Edge Triggered Interrupt Truth Table
742
DTR Edge Triggered Interrupt
743
Dtr—Data Terminal Ready
743
Table 27-5 DTR Edge Triggered Interrupt Truth Table
743
Cts—Clear to Send
744
DCD—Data Carrier Detect
744
Dsr—Data Set Ready
744
Ri—Ring Indicator
744
Programmable CTS Deassertion
744
RXD—UART Receive
744
TXD—UART Transmit
744
Figure 27-2 UART Block Diagram and Clock Generation Diagram
745
Sub-Block Description
745
Transmitter
746
Transmitter FIFO Empty Interrupt Suppression
746
Receiver
747
Idle Condition Detect Configuration
748
Idle Line Detect
748
Table 27-6 IDLE Detection Truth Table
748
Receiver Wake
749
Receiving a BREAK Condition
749
Vote Logic
749
Binary Rate Multiplier (BRM)
750
Table 27-7 Majority Vote Results
750
Baud Rate Automatic Detection Logic
752
Figure 27-4 Baud Rate Detection Protocol Diagram
752
Table 27-8 Baud Rate Automatic Detection
752
Baud Rate Automatic Detection Protocol
753
Table 27-9 Highest Baud Rates
753
Escape Sequence Detection
754
Table 27-10 Escape Timer Scaling
754
Infrared Interface
755
Programming Model
755
Table 27-11 UART Module Register Memory Map
755
UART Receiver Registers
758
Table 27-12 UART1 Receiver Register N
759
Table 27-13 UART1 Transmitter Register N and UART2 Transmitter Register N Description
760
UART Transmitter Registers
760
Table 27-14 UART1 Control Register 1 and UART2 Control Register 1 Description
761
UART Control Register 1
761
Table 27-15 UART1 Control Register 2 and UART2 Control Register 2 Description
764
UART Control Register 2
764
Table 27-16 UART1 Control Register 3 Description
767
UART2 Control Register 3
769
UART Control Register 3
767
UART1 Control Register 3
767
Table 27-17 UART1 Control Register 3 and UART2 Control Register 3 Description
769
Table 27-18 UART1 Control Register 4 and UART2 Control Register 4 Description
771
UART Control Register 4
771
Table 27-19 UART1 FIFO Control Register and UART2 FIFO Control Register Description
773
UART FIFO Control Registers
773
Table 27-20 UART1 Status Register 1 and UART2 Status Register 1 Description
775
UART Status Register 1
775
Table 27-21 UART1 Status Register 2 and UART2 Status Register 2 Description
777
UART Status Register 2
777
Table 27-22 UART1 Escape Character Register and UART2 Escape Character Register Description
779
UART Escape Character Registers
779
Table 27-23 UART1 Escape Timer Register and UART2 Escape Timer Register Description
780
UART Escape Timer Registers
780
Table 27-24 UART1 BRM Incremental Register and UART2 BRM Incremental Register Description
781
UART BRM Incremental Registers
781
Table 27-25 UART1 BRM Modulator Register and UART2 BRM Modulator Register Description
782
UART BRM Modulator Registers
782
Table 27-26 UART1 Baud Rate Count Register and UART2 Baud Rate Count Register Description
783
UART BRM Incremental Preset Registers 1–4
784
UART Baud Rate Count Registers
783
Table 27-27 UART BRM Incremental Preset Registers 1-4 Description
784
UART BRM Modulator Preset Registers 1-4
785
Table 27-28 UART BRM Modulator Preset Registers 1-4 Description
785
Table 27-29 UART1 Test Register 1 and UART2 Test Register 1 Description
786
UART Test Register 1
786
UART Operation in Low-Power System States
787
Figure 27-5 Majority Vote Results
788
Figure 27-6 Baud Rate Detection of Divisor = 1
788
Features
789
Introduction
789
Table 28-1 Endpoint Configurations
790
Chapter 28 USB Device Port 28.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1 28.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-1
791
Figure 28-1 USB Device Module Block Diagram
791
Module Components
791
Universal Serial Bus Device Controller
791
Endpoint FIFO Architecture
792
Synchronization and Transaction Decode
792
Control Logic
793
USB Transceiver Interface
793
Chapter 2 Signal Descriptions and Pin Assignments
793
Figure 28-2 USB Module Transceiver Interface
793
Pin Configuration for USB
794
Signal Description
793
Table 28-2 Pin Configuration for USB Module
794
Table 28-3 USB Module Register Memory Map
795
Programming Model
795
USB Frame Number and Match Register
796
Table 28-4 USB Frame Number and Match Register Description
796
USB Specification and Release Number Register
797
Table 28-5 USB Specification and Release Number Register Description
797
USB Status Register
798
Table 28-6 USB Status Register Description
798
USB Control Register
799
Table 28-7 USB Control Register Description
799
Table 28-8 Device Request Status
800
USB Descriptor RAM Address Register
801
Table 28-9 USB Descriptor RAM Address Register Description
801
USB Descriptor Ram/Endpoint Buffer Data Register
802
Table 28-10 USB Descriptor Ram/Endpoint Buffer Data Register Description
802
USB Interrupt Status Register
803
Table 28-11 USB Interrupt Status Register Description
803
USB Interrupt Mask Register
805
Table 28-12 USB Interrupt Mask Register Description
805
USB Enable Register
806
Table 28-13 USB Enable Register Description
806
Endpoint N Status/Control Registers
807
Table 28-14 Endpoint N Status/Control Registers Description
807
Endpoint N Interrupt Status Registers
808
Table 28-15 Endpoint N Interrupt Status Registers Description
809
Endpoint N Interrupt Mask Registers
811
Table 28-16 Endpoint N Interrupt Mask Registers Description
811
Endpoint N FIFO Data Registers
813
Table 28-17 Endpoint N FIFO Data Registers Description
813
Endpoint N FIFO Status Registers
814
Table 28-18 Endpoint N FIFO Status Registers Description
814
Endpoint N FIFO Control Registers
816
Table 28-19 Endpoint N FIFO Control Registers Description
816
Endpoint N Last Read Frame Pointer Registers
818
Table 28-20 Endpoint N Last Read Frame Pointer Registers Description
818
Endpoint N Last Write Frame Pointer Registers
819
Table 28-21 Endpoint N Last Write Frame Pointer Registers Description
819
Endpoint N FIFO Alarm Registers
820
Table 28-22 Endpoint N FIFO Alarm Registers Description
820
Endpoint N FIFO Read Pointer Registers
821
Endpoint N FIFO Write Pointer Registers
821
Table 28-23 Endpoint N FIFO Read Pointer Registers Description
821
Device Initialization
822
Programmer's Reference
822
Table 28-24 Endpoint N FIFO Write Pointer Registers Description
822
Configuration Download
823
Table 28-25 ENDPTBUF-UDC Endpoint Buffers Format
824
Enable the Device
825
Endpoint Registers
825
USB Endpoint to FIFO Mapping
825
USB Interrupt Status Register
825
Aborted Device Request
826
Exception Handling
826
Unable to Complete Device Request
826
Unable to Fill or Empty FIFO Due to Temporary Problem
826
Catastrophic Error
827
Data Transfer Operations
827
Sending Packets
827
Short Packets
827
USB Packets
827
Programming the FIFO Controller
828
Receiving Packets
828
Data Transfers to the Device
829
Data Transfers to the Host
829
USB Transfers
829
Bulk in
830
Bulk out
830
Bulk Traffic
830
Control Transfers
830
Interrupt Traffic
831
Isochronous Operations
831
Isochronous Transfers in a Nutshell
831
Interrupt Services
832
The SYNCH_FRAME Standard Request
832
USB General Interrupts
832
Msof—Missed Start-Of-Frame
832
Reset_Start—Start of USB Reset Signaling
832
Reset_Stop—End of USB Reset Signaling
832
Sof—Start-Of-Frame
832
Cfg_Chg—Host Changed USB Device Configuration
833
Frame_Match—Match Detected in USB_FRAME Register
833
SUSP—USB Suspended
833
Wakeup—Resume (Wake-Up) Signaling Detected
833
Endpoint Interrupts
833
Fifo_Empty
833
Fifo_Error
833
Fifo_Full
833
Fifo_High
833
Fifo_Low
834
Devreq—Device Request
834
Eof—End of Frame
834
Eot—End of Transfer
834
Mdevreq—Multiple Device Request
834
Interrupts, Missed Interrupts and the USB
834
Cfg_Chg
835
Devreq
835
Reset Operation
835
Hard Reset
835
UDC Reset
835
USB Software Reset
835
USB Reset Signaling
836
Interface Features
837
Overview
837
Figure 29-1 I 2 C Module Block Diagram
838
Figure 29-2 I 2 C Standard Communication Protocol
839
Clock Synchronization
840
Figure 29-3 Repeated START
840
Figure 29-4 Synchronized Clock SCL
840
Arbitration Procedure
841
Clock Stretching
841
Handshaking
841
Table 29-1 Pin Configuration
841
Table 29-2 I 2 C Module Register Memory Map
842
Programming Model
842
Table 29-3 I 2 C Address Register Description
843
Table 29-4 IFDR Register Description
844
Table 29-5 HCLK Dividers
845
Table 29-7 I2SR Register Description
848
Table 29-8 I2DR Register Description
850
Generation of START
851
Initialization Sequence
851
Post-Transfer Software Response
851
Arbitration Lost
852
Chapter 30 Synchronous Serial Interface (SSI) 30.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30-1
855
Generation of Repeated START
852
Generation of STOP
852
Slave Mode
852
SSI Architecture
855
Introduction
855
Figure 30-1 MC9328MX1 Input/Output Block Diagram
856
Figure 30-2 SSI Block Diagram
857
Figure 30-3 SSI Clocking
858
Master / Synchronous Mode
858
Normal Operating Mode
858
SSI Clock and Frame Sync Generation
858
Figure 30-4 SSI Transmit Clock Generator Block Diagram
859
Figure 30-5 SSI Transmit Frame Sync Generator Block Diagram
859
Pin Configuration for SSI
859
Pin Configuration Example Software
861
Programming Model
861
Table 30-1 Pin Configuration
861
Table 30-2 SSI Module Register Memory Map
861
SSI Transmit Data Register
862
SSI Transmit FIFO Register
863
SSI Transmit Shift Register
863
Table 30-3 SSI Transmit Data Register Description
863
Figure 30-6 Transmit Data Path (TXBIT0 = 0, TSHFD = 0)
864
Table 30-4 Data Bit Shifting Configuration
864
Figure 30-7 Transmit Data Path (TXBIT0 = 0, TSHFD = 1)
865
Figure 30-8 Transmit Data Path (TXBIT0 = 1, TSHFD = 0)
865
Figure 30-9 Transmit Data Path (TXBIT0 = 1, TSHFD = 1)
865
SSI Receive Data Register
866
SSI Receive FIFO Register
866
Table 30-5 SSI Receive Data Register Description
866
SSI Receive Shift Register
867
Table 30-6 Data Bit Shifting Configuration
867
Figure 30-10 Receive Data Path (RXBIT0 = 0, RSHFD = 0)
868
Figure 30-11 Receive Data Path (RXBIT0 = 0, RSHFD = 1)
868
Figure 30-12 Receive Data Path (RXBIT0 = 1, RSHFD = 0)
868
SSI Control/Status Register
869
Figure 30-13 Receive Data Path (RXBIT0 = 1, RSHFD = 1)
869
Table 30-7 SSI Control/Status Register Description
869
Table 30-8 I2S Mode Selection
873
SSI Transmit Configuration Register
874
Table 30-10 SSI Transmit Configuration Register Description
875
SSI Receive Configuration Register
877
Table 30-11 SSI Transmit Data Interrupts
877
Table 30-12 SSI Receive Configuration Register Description
878
Table 30-13 SSI Receive Data Interrupts
880
Table 30-14 Clock Pin Configuration
880
Table 30-15 SSI Transmit Clock Control Register and SSI Receive Clock Control Register Description
881
Calculating the SSI Bit Clock from the Input Clock Value
882
Table 30-16 SSI Bit and Frame Clock as a Function of PSR and PM in Normal Mode
883
Table 30-17 SSI Sys, Bit and Frame Clock in Master Mode
883
SSI Time Slot Register
884
Table 30-18 SSI Time Slot Register Description
884
SSI FIFO Control/Status Register
885
Table 30-19 SSI FIFO Control/Status Register Description
885
Table 30-20 Value of Transmit FIFO Empty (TFE) and Receive FIFO Full (RFF)
887
SSI Option Register
888
Table 30-21 SSI Option Register Description
888
SSI Data and Control Pins
889
SSI_RXCLK, Serial Receive Clock
889
SSI_RXDAT, Serial Receive Data
889
SSI_TXCLK, Serial Transmit Clock
889
SSI_TXDAT, Serial Transmit Data
889
Table 30-22 SSI Pin Description
889
Figure 30-14 Asynchronous (SYN = 0) SSI Configurations-Continuous Clock
890
SSI_RXFS, Serial Receive Frame Sync
890
SSI_TXFS, Serial Transmit Frame Sync
890
Figure 30-15 Synchronous SSI Configurations-Continuous and Gated Clock
891
Figure 30-16 Serial Clock and Frame Sync Timing
891
Table 30-23 SSI Operating Modes
892
Normal Mode
893
Normal Mode Receive
893
Normal Mode Transmit
893
Figure 30-17 Normal Mode Timing-Continuous Clock
894
Figure 30-18 Normal Mode Timing-Gated Clock
894
Network Mode
895
Network Mode Transmit
895
Network Mode Receive
896
Figure 30-19 Network Mode Timing-Continuous Clock
897
Gated Clock Mode
897
External Frame and Clock Operation
898
Figure 30-20 Rising Edge Clocking with Falling Edge Latching
898
Figure 30-21 Falling Edge Clocking with Rising Edge Latching
898
SSI Reset and Initialization Procedure
898
Table 30-24 SSI Control Bits Requiring Reset before Change
899
Chapter 31 CMOS Sensor Interface Module 31.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31-1
901
CSI Module Architecture
901
Introduction
901
Figure 31-1 CSI Module Block Diagram
902
Table 31-1 CSI Module Interface Signal Description
902
CSI Module Operation
903
Data FIFO Operation
903
Pin Configuration for CSI
903
Table 31-2 CMOS Interface Signals
903
Table 31-3 Pin Configuration
903
CSI Interrupt Operation
904
Register Access When CSI Module Is Disabled
904
Programming Model
904
Table 31-4 CSI Module Register Memory Map
904
CSI Control Register 1
905
Table 31-5 CSI Control Register 1 Description
905
CSI Control Register 2
908
Table 31-6 CSI Control Register 2 Description
908
CSI Status Register 1
910
Table 31-7 CSI Status Register 1 Description
910
CSI Statistic FIFO Register 1
911
Table 31-8 CSI Statistic FIFO Register 1 Description
911
CSI Rxfifo Register 1
912
Table 31-10 CSI Rxfifo Register 1 Description
912
Table 31-9 CSI Module FIFO Register Storage Scheme
912
Auto Exposure and Auto White Balance
913
Figure 31-2 Statistic Block Diagram
913
Statistic Block Diagram and Description
913
Statistic Data Generation
913
Figure 31-3 Statistic Blocks Example for 288 X 216 Pixels Image Size
914
Table 31-11 Block Size for Live View LCD Size
914
Auto Focus
915
Figure 31-4 Full Resolution Statistic Example
915
Packing of Statistic Data
915
Figure 31-5 Auto Focus Spread
916
Chapter 32 GPIO Module and I/O Multiplexer (IOMUX)
917
Sensor Interface Signals
916
Start of Frame
916
Statistic Control Signals
916
Statistic Data out
916
Statistic Data Request
916
Statistic FIFO Full
916
Statistic Output and DMA Signals
916
General Description
917
Figure 32-1 Top Level of Circuitry for Port X, Pin [I]
918
Interrupts
919
GPIO Module Features
918
GPIO Module Overview
918
GPIO Signal Description
919
Table 32-1 GPIO External Pins Description
919
GPIO Module Block Diagram
920
Pin Configuration for GPIO
920
Figure 32-2 GPIO Module Block Diagram for Port X, Pin [I]
920
Table 32-2 Pin Configuration
921
Table 32-3 GPIO Multiplexing Table with AIN, BIN, CIN, AOUT, and BOUT
922
Programming Model
923
Table 32-4 GPIO Module Register Memory Map
924
Data Direction Registers
925
Table 32-5 Data Direction Registers Description
925
Output Configuration Registers
926
Output Configuration Register 1
926
Table 32-6 Output Configuration Register 1 Description
926
Output Configuration Register 2
927
Table 32-7 Output Configuration Register 2 Description
927
Input Configuration Registers
928
Input Configuration Register A1
928
Table 32-8 Input Configuration Register A1 Description
928
Input Configuration Register A2
929
Table 32-9 Input Configuration Register A2 Description
929
Input Configuration Register B1
930
Table 32-10 Input Configuration Register B1 Description
930
Input Configuration Register B2
931
Table 32-11 Input Configuration Register B2 Description
931
Data Registers
932
Table 32-12 Data Register Description
932
GPIO in Use Registers
933
Table 32-13 GPIO in Use Register Description
933
Sample Status Registers
934
Table 32-14 Sample Status Register Description
934
Interrupt Configuration Registers
935
Interrupt Configuration Register 1
935
Table 32-15 Interrupt Configuration Register 1 Description
935
Interrupt Configuration Register 2
936
Table 32-16 Interrupt Configuration Register 2 Description
936
Interrupt Mask Registers
937
Table 32-17 Interrupt Mask Register Description
937
Interrupt Status Registers
938
Table 32-18 Interrupt Status Register Description
938
General Purpose Registers
939
Table 32-19 General Purpose Register Description
939
Software Reset Registers
940
Table 32-20 Software Reset Register Description
940
Pull_Up Enable Registers
941
Table 32-21 Pull_Up Enable Register Description
941
I 2 C Frequency Divider Register
950
Mapping Ram Registers/Memory Space
953
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