Motorola MPC8240 User Manual page 35

Table
Number
11-20 EUMBBAR Offsets for IVPRs and SVPRs.............................................................. 11-24
11-21 IVPR and SVPR Field Descriptions ......................................................................... 11-25
11-22 EUMBBAR Offsets for IDRs and SDRs .................................................................. 11-26
11-23 IDR and SDR Field Descriptions.............................................................................. 11-26
11-24 PCTPR Field Descriptions-Offset 0x6_0080......................................................... 11-27
11-25 IACK Field Descriptions-Offset 0x6_00A0 .......................................................... 11-28
11-26 EOI Field Descriptions-Offset 0x6_00B0.............................................................. 11-28
12-1 Snooping Behavior Caused by a Hit in an Internal Buffer ......................................... 12-7
12-2 Internal Arbitration Priorities.................................................................................... 12-12
13-1 MPC8240 Error Priorities ........................................................................................... 13-2
13-2 Processor Write Parity Checking ................................................................................ 13-7
14-1 Programmable Processor Power Modes ..................................................................... 14-3
14-2 Peripheral Logic Power Modes Summary ................................................................. 14-8
15-1 Memory Data Path Diagnostic Register Offsets......................................................... 15-2
15-2 Address Attribute Signal Summary ............................................................................ 15-2
15-3 Memory Address Attribute Signal Encodings ............................................................ 15-2
15-4 PCI Attribute Signal Encodings.................................................................................. 15-3
15-5 Memory Debug Address Signal Definitions............................................................... 15-6
15-6 Example of RAS Encoding For 568-Mbyte Memory System .................................... 15-8
15-7 Memory Interface Valid Signal Definition ................................................................. 15-9
15-8 DH Error Injection Mask Bit Field Definitions ........................................................ 15-18
15-9 DL Error Injection Mask Bit Field Definitions......................................................... 15-18
15-10 Parity Error Injection Mask Bit Field Definitions .................................................... 15-19
15-11 DH Error Capture Monitor Bit Field Definitions ..................................................... 15-19
15-12 DL Error Capture Monitor Bit Field Definitions...................................................... 15-20
15-13 Parity Error Capture Monitor Bit Field Definitions.................................................. 15-20
16-1 Watchpoint Signal Summary ...................................................................................... 16-2
16-2 Watchpoint Register Offsets ....................................................................................... 16-3
16-3 Watchpoint Control Trigger Register Bit Field Definitions ....................................... 16-4
16-4 Watchpoint Address Trigger Register Bit Field Definitions ...................................... 16-6
16-5 Watchpoint Control Mask Register Bit Field Definitions .......................................... 16-7
16-6 Watchpoint Address Mask Register Bit Field Definitions ......................................... 16-8
16-7 Watchpoint Control Register Bit Field Definitions .................................................... 16-9
16-8 Watchpoint Mode Select (WP_CONTROL[WP_MODE])...................................... 16-11
A-1 Address Map A-Processor View ............................................................................... A-1
A-2 Map A-PCI Memory Master View............................................................................ A-2
A-3 Address Map A-PCI I/O Master View...................................................................... A-2
B-1 Byte Lane Translation in Big-Endian Mode.................................................................B-2
B-2 Processor Address Modification for Individual Aligned Scalars .................................B-6
B-3 MPC8240 Address Modification for Individual Aligned Scalars.................................B-6
B-4 Byte Lane Translation in Little-Endian Mode ..............................................................B-6
D-1 Complete Instruction List Sorted by Mnemonic.......................................................... D-1
D-2 Complete Instruction List Sorted by Opcode............................................................... D-9
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