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Table 6-6. SDRAM Address Multiplexing SDBA[1:0] and
msb
Row x Col x Bank
0-4
11x10x2
SDRAS
SDCAS
11x9x2
SDRAS
SDCAS
13x10x2
SDRAS
SDCAS
13x9x2
SDRAS
SDCAS
12x10x4
SDRAS
SDCAS
12x9x4
SDRAS
SDCAS
Table 6-7 shows the multiplexing of the internal physical addresses A[0
SDBA[1:0] and SDMA[12:0] during the row and column phases of the 64-bit mode. The
shaded cells in Figure 6-7 are the unspecified bits.
SDMA[12:0]—32-Bit Mode
1
1
1
5 6
7 8 9
0
1
2
B
1
9
8
A
0
0
9 B
A
0
B
1
9
8
A
0
0
B
A
0
1
1
B
1
9
8
1
2
A
0
0
9
B
A
0
1
1
B
1
9
8
2
1
A
0
0
B
A
0
1
B
B
1
9
8
1
A
A
0
1
0
9
B
B
A
A
1
0
1
B
B
1
9
8
1
A
A
0
1
0
B
B
A
A
1
0
Chapter 6. MPC8240 Memory Interface
Physical Address
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SDRAM Interface Operation
2
2
2
2
2
2
2
2
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
:1
] through
msb
lsb
lsb
2
3
3
9
0
1
0
0
0
0
0
0
6-11
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