Interrupt Request Register (Irr) - Motorola MPC8240 User Manual

EPIC Pass-Through Mode
During an EOI cycle, the value in the in-service register (ISR) is used to select which bits
are to be cleared in the ISR. One cycle after an EOI cycle, the output of the IS contains the
interrupt source identification and priority value to be cleared from the ISR. This interrupt
source is the one with highest priority in the in-service register.

11.3.6.3 Interrupt Request Register (IRR)

The interrupt request register (IRR) always passes the output of the IS except during
interrupt acknowledge cycles. During interrupt acknowledge cycles, interrupts in the IS and
IPR are not propagated to guarantee that the vector that is read from the interrupt
acknowledge register is not changing due to the arrival of a higher priority interrupt. The
IRR also serves as a pipeline register for the two-clock propagation time through the IS.
11.3.6.4 In-Service Register (ISR)
The contents of the in-service register (ISR) are the priority and source values of the
interrupts that are currently in service in the processor. The ISR receives an internal bit-set
command during interrupt acknowledge cycles and an internal bit-clear command during
EOI cycles.
11.4 EPIC Pass-Through Mode
The EPIC unit provides a mechanism to support alternate external interrupt controllers such
as the PC-AT-compatible 8259 interrupt controller. After a hard reset, the EPIC unit defaults
to pass-through mode. In this mode, interrupts from external source IRQ0 are passed
directly to the processor; thus, the interrupt signal from the external interrupt controller can
be connected to IRQ0 to cause direct interrupts to the processor. Note that IRQ0/S_INT is
an active-high signal. Note also that the EPIC unit does not automatically perform a vector
fetch from an 8259 interrupt controller.
When pass-through mode is enabled, none of the internally generated interrupts are
forwarded to the processor. However, in pass-through mode, the EPIC unit passes the raw
2
interrupts from the global timers, MU (including DMA controllers), and I C to the L_INT
output signal.
2
If the interrupts from the global timers, MU (including DMA controllers), and I C are
required to be reported internally to the processor, pass-through mode must be disabled. If
pass-through mode is disabled, the internal and external interrupts are delivered using the
priority and delivery mechanisms otherwise defined for the EPIC unit.
The pass-through mode is controlled by the GCR[M] bit (enabled when GCR[M] = 0).
Note that when switching the EPIC unit from pass-through to mixed mode (either direct or
serial), the programming note in Section 11.8, "Programming Guidelines," may apply.
11-10 MPC8240 Integrated Processor User's Manual