Motorola MPC8240 User Manual page 30

Integrated host processor with integrated pci
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Figure
Number
E-17
DSISR .........................................................................................................................E-19
E-18
Machine Status Save/Restore Register 0 (SRR0)
Machine Status Save/Restore Register 1 (SRR1) .......................................................E-19
E-19
Machine Status Save/Restore Register 1 (SRR1) .......................................................E-19
E-20
Decrementer Register (DEC)......................................................................................E-20
E-21
External Access Register (EAR).................................................................................E-20
E-22
DMISS and IMISS Registers ......................................................................................E-21
E-23
DCMP and ICMP Registers........................................................................................E-21
E-24
HASH1 and HASH2 Registers ...................................................................................E-22
E-25
Required Physical Address Register (RPA) ...............................................................E-22
E-26
Instruction Address Breakpoint Register (IABR).......................................................E-23
E-27
Hardware Implementation Register 0 (HID0) ............................................................E-24
E-28
Hardware Implementation Register 1 (HID1) ............................................................E-27
E-29
Hardware Implementation-Dependent Register 2 (HID2)..........................................E-28
xxx
ILLUSTRATIONS
Title
MPC8240 Integrated Processor User's Manual
Page
Number

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