Rom/Flash Interface Write Timing - Motorola MPC8240 User Manual

ROM/Flash Interface Operation

6.4.5 ROM/Flash Interface Write Timing

The parameter MCCR1[ROMNAL] controls the Flash memory write recovery time (that
is, the number of cycles between write pulse assertions). The actual recovery cycle count is
four cycles more than the value specified in ROMNAL. For example, when ROMNAL =
0b0000, the write recovery time is 4 clock cycles; when ROMNAL = 0b0001, the write
recovery time is 5 clock cycles; when ROMNAL = 0b0010, the write recovery time is 6
clock cycles; and so on. ROMNAL is set to the maximum value at reset. To improve
performance, initialization software should program a more appropriate value for the
device being used.
Figure 6-61 shows the write access timing of the Flash interface.
MCLK
A[0:19]
CS
FOE
WE
DATA D0
2 cycles ROMFAL 4 cycles ROMNAL
(constant) (minimum)
Figure 6-61. 8-, 32-, or 64-Bit Flash Write Access Timing
6.4.6 PCI-to-ROM/Port X Transaction Example
The figures in this section provide examples of signal timing for PCI-to-ROM/Port X
transactions. Figure 6-62 shows a series of PCI reads from ROM/Port X(64-Bit).
Figure 6-63 shows a series of PCI reads from ROM/Port X (8-Bit).
6-84 MPC8240 Integrated Processor User's Manual