Motorola MPC8240 User Manual page 619

Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this
book. Some of the terms and definitions included in the glossary are reprinted from IEEE
Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, copyright ©1985 by
the Institute of Electrical and Electronics Engineers, Inc. with the permission of the IEEE.
A
Atomic. A bus access that attempts to be part of a read-write operation to the
B
Beat. A single state on the 603e bus interface that may extend across multiple
Big-endian. A byte-ordering method in memory where the address n of a
Burst. A multiple beat data transfer whose total size is typically equal to a
Bus clock. Clock that causes the bus state transitions.
Bus master. The owner of the address or data bus; the device that initiates or
C Cache. High-speed memory containing recently accessed data and/or
same address uninterrupted by any other access to that address (the
term refers to the fact that the transactions are indivisible). The
PowerPC 603e microprocessor initiates the read and write
separately, but signals the memory system that it is attempting an
atomic operation. If the operation fails, status is kept so that the 603e
can try again. The 603e implements atomic accesses through the
lwarx/stwcx. instruction pair.
bus cycles. A 603e transaction can be composed of multiple address
or data beats.
word corresponds to the most significant byte. In an addressed
memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0
being the most significant byte.
cache block (in the 603e, a 32-byte block).
requests the transaction.
instructions (subset of main memory).
Glossary of Terms and Abbreviations Glossary-1