Motorola MPC8240 User Manual page 494

Memory Interface Valid (MIV)
SDRAM_
CLK[0:3]
ts
CKE
RAS/CS
SDRAS
SDCAS
CAS/DQM
ADDRESS
DRAM
DATA
WE
DEBUG
ADDRESS
MIV
MAA
Figure 15-13. Example SDRAM Debug Address, MIV, and MAA Timings for Burst
15-14
ACTORW
ROW
D0 D1
VALID
VALID
Write Operation
MPC8240 Integrated Processor User's Manual
COL
D2 D3
ROW