Motorola MPC8240 User Manual page 219

Chapter 6
MPC8240 Memory Interface
The MPC8240 integrates a high-performance memory controller that controls processor
and PCI interactions to local memory. The MPC8240 supports various types of DRAM and
ROM/Flash configurations as local memory.
• SDRAM
— SDRAMs must comply with the JEDEC specification for SDRAM
— High-bandwidth bus (32- or 64-bit data bus) to SDRAM
— One-Mbyte to 1-Gbyte SDRAM memory—1 to 8 chip selects for SDRAM bank
sizes ranging from 1 Mbyte to 128 Mbytes per bank
— Supports page mode SDRAMs—four open pages simultaneously
— Programmable timing for SDRAMs
• DRAM—fast page mode (FPM) and extended data out (EDO)
— High-bandwidth bus (32- or 64-bit data bus) to DRAM
— One-Mbyte to 1-Gbyte DRAM memory space
— One to eight chip selects of 4-, 16-, 64- or 128-Mbit memory devices
— Programmable timing for FPM and EDO
• ROM/Flash
— 16 Mbytes of ROM/Flash space can be divided between the PCI bus and the
memory bus (8 Mbytes each)
— Supports 8-bit asynchronous ROM or 64-bit burst-mode ROM
— Configurable data path—8-, 32-, or 64-bit
— Supports bus-width writes to Flash
• Port X—The ROM/Flash controller can interface any device that can be controlled
with an address and data field (communication devices, DSPs, general purpose I/O
devices, or registers). Some devices may require a small amount of external logic to
properly generate address strobes and chip selects.
— 8-bit Port X
— 32-bit Port X
— 64-bit Port X—the floating-point (FPU) unit must be enabled for 64-bit writes
Chapter 6. MPC8240 Memory Interface 6-1