Motorola MPC8240 User Manual page 186

PowerPC Processor Core Features
• Five independent execution units and two register files
— BPU featuring static branch prediction
— A 32-bit IU
— Fully IEEE 754-compliant FPU for both single- and double-precision operations
— LSU for data transfer between data cache and GPRs and FPRs
— SRU that executes condition register (CR), special-purpose register (SPR), and
integer add/compare instructions
— Thirty-two GPRs for integer operands
— Thirty-two FPRs for single- or double-precision operands
• High instruction and data throughput
— Zero-cycle branch capability (branch folding)
— Programmable static branch prediction on unresolved conditional branches
— BPU that performs CR lookahead operations
— Instruction fetch unit capable of fetching two instructions per clock from the
instruction cache
— A six-entry instruction queue that provides lookahead capability
— Independent pipelines with feed-forwarding that reduces data dependencies in
hardware
— 16-Kbyte data cache—four-way set-associative, physically addressed, LRU
replacement algorithm
— 16-Kbyte instruction cache—four-way set-associative, physically addressed,
LRU replacement algorithm
— Cache write-back or write-through operation programmable on a per page or per
block basis
— Address translation facilities for 4-Kbyte page size, variable block size, and
256-Mbyte segment size
— A 64-entry, two-way set-associative ITLB
— A 64-entry, two-way set-associative DTLB
— Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte
blocks
— Software table search operations and updates supported through fast trap
mechanism
— 52-bit virtual address; 32-bit physical address
5-4 MPC8240 Integrated Processor User's Manual